Multiple spi messages with dma

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DaRi_1490761
Level 1
Level 1

Hi,

I'm using the w5500 ethernet IC with the psoc5.

To send data over the internet i need to write data, update some write pointers and give the send command.

I have configured a dma channel with 3 chains so all the messages are send behind each other. This works fine.

My problem is that the chip select Line stays low between the messages so my chip is seeing 1 message so IT doesn't work.

Is IT possible to have the chip select high for a clock cycle when the TD is finished and back low when the next TD begins?

The channel is terminated when the last TD is executed.

The goal is when i enable the channel, all instructions are send automaticly and receive the data on my computer.

I can't find any examples, most of Them are sending a single message.

Does anybody knows how to Fix this?

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1 Solution

len,

thank you for your message.

my DMA drq is connected to the tx_interrupt pin with only "interrupt on tx fifo empty" checked.

I tried your configuration but my SS went high after each byte of data (DMA burst set to 1 byte).

This was fixed after changing the request_per_burst from 1 to 0. i found this on another forum (If the parameter REQUEST_PER_BURST is set to zero then the DMA will transfer number of bytes as specified by TD)

thank you for helping me in the right direction!

Danny

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3 Replies
Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

danny,

Using a DMA with SPI is a great thing! (Love the PSoC!).  What are you you using for your DMA drq?  In order to get the SS line to go from active low to inactive high for each SPI transfer, you need to select "Enable TX Internal Interrupt" and then "Interrupt On SPI Idle" ONLY.  The SPI idle flag occurs when ALL the SPI data in the SPI FIFO is sent.  This will cause the SS line to go inactive high.  Your DMA drq is attached to the tx_intterrupt with this interrupt only set.

All the other interrupt sources can cause the next SPI data to be loaded immediately so the SS line will remain active low.

Len

Len
"Engineering is an Art. The Art of Compromise."

len,

thank you for your message.

my DMA drq is connected to the tx_interrupt pin with only "interrupt on tx fifo empty" checked.

I tried your configuration but my SS went high after each byte of data (DMA burst set to 1 byte).

This was fixed after changing the request_per_burst from 1 to 0. i found this on another forum (If the parameter REQUEST_PER_BURST is set to zero then the DMA will transfer number of bytes as specified by TD)

thank you for helping me in the right direction!

Danny

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Danny,

My pleasure!

Len

Len
"Engineering is an Art. The Art of Compromise."
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