5 Replies Latest reply on Jul 4, 2019 3:33 AM by HemanthR_06

    FX3 PCLK direction and frequency

    doruc_1309621

      Hi,

       

      Our goal is to set PCLK clock direction to output and set it to be lower than 100MHz.

       

      We have changed "Clock setting" to "Internal" in GPIF designer and everything seems to be working fine with 100MHz clock settings, but when clkDiv value is increased in CyFxSlFifoApplnInit() function, design is no longer working. 

       

      PCLK frequency was measured with oscilloscope and it decreases as expected when clkDiv value is changed, but design does not work in any other frequency except 100Mhz (we tried 25Mhz, 50Mhz, 80MHz).

       

      Is there anything else to be changed/modified in order to change PCLK frequency?

        • 1. Re: FX3 PCLK direction and frequency
          NoriakiT_91

          Did you use the function CyU3PPibInit() to specify the PCLK frequency?

          I have configured the PIB clock to 25kHz with the following context.

           

              /* Initialize the p-port block. */
              pibClock.clkDiv = 1000;                     // 25MHz/1000=25kHz
              pibClock.clkSrc = CY_U3P_SYS_CLK_BY_16;     // 25MHz
              pibClock.isHalfDiv = CyFalse;
              /* Disable DLL for sync GPIF */
              pibClock.isDllEnable = CyFalse;
              apiRetStatus = CyU3PPibInit(CyTrue, &pibClock);
          

           

          The PIB clock is used to blink an LED at CTRL4 with following state machine.

           

          GS004120.png

          Please refer my github repository at GitHub - noritan/LedBlink: An example project blinking a LED powered by GPIF II state machine on FX3. if you are interested in my project.   I don't know if this project can be used now because it supported FX3 SDK V1.2.3

           

          Regards,

          Noriaki

          • 2. Re: FX3 PCLK direction and frequency
            doruc_1309621

            yes I did, here is my part of code:

             

            /* Initialize the p-port block. */
            pibClock.clkDiv = 5;
            pibClock.clkSrc = CY_U3P_SYS_CLK;
            pibClock.isHalfDiv = CyFalse;
            /* Disable DLL for sync GPIF */
            pibClock.isDllEnable = CyFalse;
            apiRetStatus = CyU3PPibInit(CyTrue, &pibClock);
            

             

            with pibClock.clkDiv = 5; I am getting 80MHz PCLK frequency (measured with oscilloscope) but data transfer does not work properly. If I change to pibClock.clkDiv = 4; everything works fine. 

             

            Does GPIF project in GPIF designer has to be modified somehow in order to work with different frequency or am I missing something else?

            • 3. Re: FX3 PCLK direction and frequency
              HemanthR_06

              Hi,

               

              GPIF Designer project need not be changed for different PCLK frequencies.

               

              Regards,

              Hemanth

              • 4. Re: FX3 PCLK direction and frequency
                NoriakiT_91

                I have created an example project sending data stream received from BULK-OUT into the 32-bit GPIF.  A tiny GPIF state machine is created and contained in the project.  Please note that this project has a BULK-IN in the configuration descriptor but it is not implemented.

                 

                The data transfer rate is measured by the C++ Streamer installed with the FX3 SDK.  The configuration of the C++ streamer is the default, 32 Packets per Transfer, 16 Transfers to Queue.  Following is the transfer rate measured by C++ Streamer.

                 

                clkDivPIB Clock (kHz)Ideal Transfer Rate (kB/s)Measured Transfer Rate (kB/s)
                2200,000800,000320,200
                3133,333533,333325,300
                4100,000400,000325,800
                580,000320,000262,600
                666,666266,666243,300
                850,000200,000184,900
                1625,000100,00095,900
                3212,50050,00048,700
                646,25025,00024,300
                1283,12512,50012,100
                2561,5626,2506,000

                 

                It was found that the measured transfer rate is proportional to the PIB Clock when the transfer rate is lower than 320MB/s.

                 

                Regards,

                Noriaki

                • 5. Re: FX3 PCLK direction and frequency
                  HemanthR_06

                  Hi,

                   

                  Can you please also check the below KBA:

                  Configuring EZ-USB® FX3™ GPIF-II DLL - KBA210733

                   

                  Also refer to AN87216 source code of Master. Here the DLL configuration is made - see function CyFxApplnSetPibDllParameters(). (In this example the PCLK would be 100MHz.) You will have to change it (as per Table 2 in the KBA mentioned above) based on your desired PCLK.

                   

                  Regards,

                  Hemanth