1 2 Previous Next 15 Replies Latest reply on Jul 19, 2019 2:16 AM by SrinathS_16

    fx3 reset issue

    JoSc_1279791

      We have a custom board including an FX3 and a Xilinx Kintex Ultrascale device. The FX3 is connected to I2C EEPROMs (24FC1025-I/SM) for boot purposes. The pmode pins are set to "I2C boot with USB fall-back). The RESET_n pin of the FX3 is connected to one of the Xilinx GPIOs as well as to a push button with a weak pull-up (20k).

       

      During JTAG loading of the Xilinx, I noticed that  sometimes the FX3 would come up with the bootloader PID, indicating that it hadn't booted from I2C as expected. So I included  a startup state machine to hold the RESET_n pin low for 10ms at power up, but that seems to fail some times as well. The indication is always that the FX3 comes up with the bootloader PID (04b4:00f3). At that point, even pressing the push button (which grounds the reset pin) doesn't seem to help and the only resolution is to power cycle the board.

       

      Any ideas what could be happening there? Are there any conditions on how the RESET_n needs to be asserted?

        • 1. Re: fx3 reset issue
          NoriakiT_91

          It seems that the I2C boot sequence failed to start with the bootloader.

           

          What is the I2C bus clock speed?

          The I2C speed is specified by the 3rd byte of the I2C EEPROM.

          If you specified higher I2C speed like 1MHz, please try with slower clock speed.

           

          Regards,

          Noriaki

          • 2. Re: fx3 reset issue
            JoSc_1279791

            I am compiling the I2C image with the flag "-i2cconf 1E". So if I interpret the manual correctly, this should mean that the I2C speed bits are 01, which should put the speed at 400kHz. This doesn't seem to be the issue.

            • 3. Re: fx3 reset issue
              SrinathS_16

              Hello,

               

              - Have you built the firmware IMG file through the Eclipse IDE?

              - Did you program the IMG file onto the EEPROM through the Cypress USB Control Center?

              - Are there any activities on the I2C lines during the boot-up of FX3?

              - FX3 RESET pin needs to be de-asserted for the boot-loader to run. So, only after the RESET pin is de-asserted, the FX3 boot-loader loads the firmware from the EEPROM.

              - Is the RESET pulse de-asserted at least 1ms after the VCC supply is stable?

               

              Best regards,

              Srinath S

              • 4. Re: fx3 reset issue
                JoSc_1279791

                - Yes, the image has been built through the Eclipse IDE

                - Yes, the image has been programmed through the Cypress USB Control Center

                - I have not checked yet any specifics of the I2C transactions during boot, but I do see I2C activity

                -

                - The reset is de-asserted 100ms after power up, so that should be plenty of time for he VCC to be stable

                • 5. Re: fx3 reset issue
                  SrinathS_16

                  Hello,

                   

                  - Please check the I2C lines for any activity during boot-up. Are the initial 'CY' signature bytes sent successfully?

                  - Have you used an EEPROM that has been mentioned in the AN76405 and ensured that the bits are correspondingly set?

                   

                  Best regards,

                  Srinath S

                  • 6. Re: fx3 reset issue
                    JoSc_1279791

                    We are using two Microchip 24FC1025-I/SM memories to store the image for the FX3. Those are operated at 1.8V. The bits set in the image are 0x1E, which means the I2C transactions are at 400kHz, 128kB memory, which sounds correct to me.Also, when I don't do the reset, the boot seems to complete correctly, so the image must be correct. I have checked that I see I2C activity during boot, but have not analyzed the individual transactions, yet.

                    • 7. Re: fx3 reset issue
                      NoriakiT_91

                      Please let me confirm the size of .img file.

                      If the size is larger than 128kB, multiple I2C EEPROMs are required to store the binary.

                       

                      Regards,

                      Noriaki

                      • 8. Re: fx3 reset issue
                        JoSc_1279791

                        Yes, that is correct. We are using two of these devices, with the address bits set accordingly

                        • 10. Re: fx3 reset issue
                          NoriakiT_91

                          I found an old document in 2011 which is obsoleted now.

                          GS004180.png

                          It seems that the connection of the address pins are correct.

                          Please let me confirm if the VIO5 is connected to the 1.8V power supply.

                           

                          Regards,

                          Noriaki

                          • 11. Re: fx3 reset issue
                            JoSc_1279791

                            Yes, VIO5 (as well as VIO1_1, VIO1, VIO2, VIO3, VIO4) are all connected to 1.8V

                            • 12. Re: fx3 reset issue
                              SrinathS_16

                              Hello,

                               

                              - Can you please provide more information on the below statement? Kindly, explain the sequence followed.

                              "Also, when I don't do the reset, the boot seems to complete correctly"

                               

                              - When the failure is happening, please capture the I2C line captures and let me know the observations.

                               

                              Best regards,

                              Srinath S

                              • 13. Re: fx3 reset issue
                                JoSc_1279791

                                What is meant by this statement is the following:

                                 

                                Our design has an FPGA pin connected to the RESET_n line of the FX3. When I tri-state this pin, so that now signal if going from the FPGA to the FX3 RESET_n, then the boot process succeeds.

                                 

                                I will try to attach a scope to the I2C lines and will let you know what I observe, might be a few days until I can get to that, though.

                                • 14. Re: fx3 reset issue
                                  JoSc_1279791

                                  I looked at the SDA pin on the EEPROM for the two different cases:

                                  This first picture is when boot was working. One can see the I2C transaction starting at power up, then there is a small pause, and then it loads again:

                                  DSC_0832.JPG

                                   

                                  Here then is the picture, when the boot fails after the reset from the FPGA:

                                   

                                  DSC_0831.JPG

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