5 Replies Latest reply on Jun 20, 2019 8:41 AM by JoWi_3984961

    clock stops!


      How good is the phase locked loop on the PSOC 4?

      I'm seeing clock stop for a tiny bit every so often.

      I see you have an issue here:




      Output behavior of CY22393 (or CY22381, CY22392, CY22394, CY22395) in case of lost reference clock on XTALIN pin


      But, is the same IP used in the phase locked loop on PSOC 4?

      I only change the divisor and the fractional divisor.

      I never stop it.

      It is set to start up automatically in the system-wide resources.


      Is there an errata on this? An application note? Any document?


      What if we reference our clock to a USB device?

      A crystal?


      Which is most reliable?


      Need some external reference.