1 Reply Latest reply on Jun 13, 2019 10:43 AM by ShivendraS_56

    FM25CL64B-G: Block protection bits BP1 and/or BP0 set randomly after write

    JoWi_4298601

      Hi,

       

      we are having issues with BP1 and/or BP0 being set seemingly random after a write to the FRAM occured. We have one board design with said FRAM chip and it occures on all of the tested boards to date (around 5). We checked the supply voltage and SPI and everything looks good to us. We also checked the SPI signals for noise, but this also looks good.

      Signals.PNG

      This shows two write sequences that consist of checking for the block protection bits followed by the write to the FRAM. After the first write both block protection bits are set and we cannot figure out why. The block protection bits are set randomly after any write. So not necessarily after the first. We have 4 writes every few seconds.

       

      Supply was measured close to the FRAM

      Board.PNG

      Schematic.PNG

      We tried hard to find an issue in the supply voltage or communication with the FRAM. Is there something obvious we missed? Could this be a result of too much heat during board production? We have yet to check if the write operation before the protection bits are set were successful.

       

      Attached you can find a .psdata file that you can open with the free Picoscope 6 application to have a close look a the signals.

        • 1. Re: FM25CL64B-G: Block protection bits BP1 and/or BP0 set randomly after write
          ShivendraS_56

          Hi Johannes,

          Please check if the controller SPI mode is set correctly (0 or 3).

          Write to memory is opcode 0x02 and write to status register is 0x01. If by any chance opcode 0x02 is right shifted by 1 during the transmission, the device would latch wrong opcode and end up executing the SR write, instead of memory write.

           

          To further verify, if memory write causes register write in FRAM, you can try with the following:

           

          1- Write SR with data 0x08; read and verify

          2- Write to memory with 0x00 data pattern at address location 0. If the memory write falsely triggers register write then read SR will return 0x00. Reading memory from 0 will return with old content.

          3- Repeat step 2 with write to memory with 0xFF pattern at location 0. If the memory write falsely triggers register write then read SR will return 0x8C. Reading memory from 0 will return with old content.

           

          When you execute memory read after intended write, does it return the same old data or does read data change?

           

          Thanks,

          Shivendra