3 Replies Latest reply on Jun 11, 2019 11:28 PM by YangyangC_06

    How to configure the MIPI Receiver in CX3 ?

    user_62720120

      I'm not sure how to configure the MIPI Receiver for the CX3.

      My camera is the OV7251. It has a resolution of 640x480 at 120FPS and 10-bit monochrome raw pixels. 1 MIP lane.

       

      1. What should the values of V and H blanking be? nothing about blanking is mentioned in the datasheet of the image sensor.

      2. What should be the values of THS Prepare and Zero?

      3. Do I have to set the CSI Clock value to the *exact* correct value? What if the image sensor clock is not exactly correct?

      4. Should my Output pixel clock equal 36,864,000 (640x480x120) ?

      5. What should be the Fifo delay?

      6. Is there somewhere a document that explains all of this? I have read several Cypress documents, including the FX3 and CX3 TRMs, and the AN75779 and AN90369, but they didn't seem to help me find the answers.

       

      Many thanks

      Hugo

        • 1. Re: How to configure the MIPI Receiver in CX3 ?
          YangyangC_06

          Hello,

           

          • You need to consult with sensor FAE to get the values of of H_blanking ,V_blanking ,THS_zero and THS_prepare.
          • You don't need set the CSI clock to *exactly* same to the real value. Most of the values shown in this configuration tools are adjustable. For example, if you set CSI clock to 300 MHz(while the real value is 305 MHz) and the correpsonding FIFO dealy is 200 bytes, it may work since you could change FIFO delay to a smaller value. You could change other values to cover this  mismatch.
          • You could refer to this KBA

                 Streaming RAW10 Format Input Data to 16/24-bit Output Format in CX3 MIPI CSI-2 - KBA224387

          • The valus between the min and max are all acceptable.

          Hope it helps.

          • 2. Re: How to configure the MIPI Receiver in CX3 ?
            user_62720120

            Thanks for the reply,

             

            • You don't need set the CSI clock to *exactly* same to the real value. Most of the values shown in this configuration tools are adjustable. For example, if you set CSI clock to 300 MHz(while the real value is 305 MHz) and the correpsonding FIFO dealy is 200 bytes, it may work since you could change FIFO delay to a smaller value. You could change other values to cover this  mismatch.

             

            I meant something slightly different.  Let me give an example to illustrate.  In the PSoC, when configuring an I2C slave for example, I can set the clock speed. This doesn't have to match the exact speed that the I2C master will use, it just has to be sufficiently high.

             

            Perhaps the MIPI receiver is similar? This is a similar situation after all, we have a clock and data line in MIPI, as we do in I2C.

             

            My other point is this:

             

            If the oscillators driving the CX3 and the Image sensor are each accurate to 100ppm, then they will never be *exactly* the same. Perhaps the Image sensor will be producing pixels slightly faster than the CX3 pixel clock? Or perhaps the CX3 pixel clock will be a tiny bit faster than the image sensor is producing pixels?  How is this situation handled?

             

            Many thanks

            Hugo

            • 3. Re: How to configure the MIPI Receiver in CX3 ?
              YangyangC_06

              Hugo Elias 撰写:

               

              Thanks for the reply,

               

              • You don't need set the CSI clock to *exactly* same to the real value. Most of the values shown in this configuration tools are adjustable. For example, if you set CSI clock to 300 MHz(while the real value is 305 MHz) and the correpsonding FIFO dealy is 200 bytes, it may work since you could change FIFO delay to a smaller value. You could change other values to cover this  mismatch.

               

              I meant something slightly different.  Let me give an example to illustrate.  In the PSoC, when configuring an I2C slave for example, I can set the clock speed. This doesn't have to match the exact speed that the I2C master will use, it just has to be sufficiently high.

               

              Perhaps the MIPI receiver is similar? This is a similar situation after all, we have a clock and data line in MIPI, as we do in I2C.

               

              Please try your best to set the CSI clock value to the real one. If you set a much bigger number, the tool may not find a suitable PCLK and FIFO delay.

               

              My other point is this:

               

              If the oscillators driving the CX3 and the Image sensor are each accurate to 100ppm, then they will never be *exactly* the same. Perhaps the Image sensor will be producing pixels slightly faster than the CX3 pixel clock? Or perhaps the CX3 pixel clock will be a tiny bit faster than the image sensor is producing pixels?  How is this situation handled?

              You don't need the take care about the issue in ppm level. As I said before, the mistach of clock speed could be covered by adjusting other parmaters such as PCLK and FIFO delay. Please comapare the two screenshoots below.

               

              BaiduShurufa_2019-6-12_14-21-47.png

               

              BaiduShurufa_2019-6-12_14-22-16.png