fx2lp isochronous aadj with 512 quad buffering and 2 additional transactions per microframe

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HSo_3703166
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Probably answering the question myself, the TRM states that the aadj=1 will check only 1024byte commited buffers but I was wondering if it should work also on 512byte packets /fifo buffers for IN(2) endpoints. It doesn't seem to work with me so I was wondering if it is suposed to or if by design it doesn't, then, is there any sample on how to do the pid sequencing in the firmware? I need the quad buffering and (512*3)*8

Thank you in advance.

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Hello,

As per my understanding, you could commit data in packets of 512 and setting AADJ=1 in this mode with INPPF=1 is sending one packet(either data or zlp) in each microframe with DATA0. You could achieve more than 512 bytes in one microframe with AADJ=0 but that will not maintain the sequencing if any microframe contains lesser bytes.

Another option is to set 2x1024 for EP2 (please check figure 1-17 in TRM) with AADJ=1 and INPPF=2 which will maintain the sequence and send two packets(either data or zlp) in each microframe. Please let me know if this isnt feasible for your application to commit in packets of 1024 instead of 512.

Best Regards,

Sananya

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Sananya_14
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750 replies posted 500 replies posted 250 solutions authored

Hello,

We checked for few test cases and found that if you set AADJ=0 and send (512*3)*8 packets, the sequence will still be intact. However you should ensure that the buffer always has 512 byte packets to maintain the sequence. The EPxISOINPKTS register considers any length less than 1024 as short packet and hence will send each packet as DATA0 if AADJ=1.

Best Regards,

Sananya

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Well, thats exactly the behavior I am experiencing but unfortunately is not possible to keep the buffers full in the application. You see I am trying to stream audio full duplex with iso in2 and iso6 out and the audio adc/dac provides the sampling rate because it is the master clock, so only when there is enough data to move from the adc to the usbhost(pc) there will be a commited packet, and the rest of the time it must keep sending zlp's. The host driver checks when there are enough samples arrived and collected and this is the throttle for the out endpoint so the host sends only the exact amount of samples that have been received to stay in sync. Hence the importance of the zlp's.  Because nor the host driver nor the fpga feeding the fifos know or have any influence on the variable sampling rate, the amount of zlp's is variable also. Unfortunately the (2x1024)*8 option is out of the question because the fx2lp only has 2 x1024 buffs in bidirectional mode. It seems so the only alternative is to use AADJ=0 and INPPF[1:0]=1 but then if I ask the driver to work this way, I only will get 512 bytes per micro frame.  Any other sugestion for additional transfers in 512 quad mode?

Regards,

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Hello,

As per my understanding, you could commit data in packets of 512 and setting AADJ=1 in this mode with INPPF=1 is sending one packet(either data or zlp) in each microframe with DATA0. You could achieve more than 512 bytes in one microframe with AADJ=0 but that will not maintain the sequencing if any microframe contains lesser bytes.

Another option is to set 2x1024 for EP2 (please check figure 1-17 in TRM) with AADJ=1 and INPPF=2 which will maintain the sequence and send two packets(either data or zlp) in each microframe. Please let me know if this isnt feasible for your application to commit in packets of 1024 instead of 512.

Best Regards,

Sananya

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Well again thank you very much for your time with this legacy device issue. The behavior I see with 2x1024 and ep2@2x1024 per microframe(uF) is that when the uF gets serviced, only one buffer is committed ( because the adc is filling the other buffer) and the additional xfer wont take place. Because my data rate is aprox1300bytes per uF, the 2nd buffer gets commited with only with 300bytes (using pktend signal) and for the next uF only one buffer with 300bytes is available. At this point in time I run out of buffering and cannot push any samples more in the fx2lp. As you can see I can only send 1300 bytes in 2 uF instead of 2600bytes, showing the granularity issue of 2x1024 against 4x512 and that in my case with a datarate of 1300bytes per uF using 1024buffs leads to a dead space of 742b while using 512buffs only 236bytes. If the 3x512 was possible I could send 512,512,276 per uF and still have the 4th buffer to avoid running out of space.  In any case I see now that fx2lp is not the right choice atm. The only thing I can think of is try to add extra fifos to create the quad buffering (extend the 2x1024 outside) but that implies another cpld/fpga.

Regards.

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Hello,

If you would like extra buffer for the ADC to fill data in so that you can have data available for the next microframe, you could set INPPF=3 and AADJ=0. The FX2LP buffering can be set as triple buffering of 512 bytes each. Other than this, I dont think there is any way other than using external FIFOs.

You could also increase your polling interval to allow complete 1300 bytes to be sent within one microframe.

Best Regards,
Sananya

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