1 Reply Latest reply on Jun 6, 2019 10:48 PM by PradiptaB_11

    Minimum Chip deselect time TCS

    user_63856

      I'm working with CY15B116QSN device using 002-26981 preliminary datasheet.

      I've developed a VHDL FRAM access engine and now i'm simulating the FRAM behaviour. I'm using QSPI access @ 67,5MHz.

       

       

      In the table AC switching caracteristic of device CY15B116QSN i'have seen we need to meet tcs chip deselect time.

      that is described as: "the minimum chip deselect (CS_HIGH) time before the new command cycle starts in a specific SPI mode. This parameter ensures that previous operation is successfully completed before the host start a new command cycle"

      i follow this spec during Register access to setup the CR1, CR2 and CR5 register.

      My question is:

      Have i to respect it if i would access to Memory content using only the commands:

      - 0x02 (memory write) and

      - 0x03 (memory read) ?

      If yes which time i have to follow ? 110 ns ?

       

      BR/

      Marco