7 Replies Latest reply on Nov 10, 2019 11:35 PM by KandlaguntaR_36

    440MHz in PLL Out Clock is not possible. Denebola Kit

    IvPe_4204671

      Hello to everybody.


      I am new to CX3 and using the CX3 Configuration Project. It is not possible for me to configure an exact 400MHz PLL Out Clock of as of the 19.2MHz ref clock in the Denebola Evaluation Board. I mean, it is not possible to reach a round number of 440MHz by selecting different values from Pre Divider Value, PLL OutRange and Multiplier of Unit Clk. however is possible to get a very close value of 440.12MHz.

       

      Can anybody tell me how equal this Clock and the Sensor MIPI Output clock should be? Could I enter in a Over/Underflow ?

       

      Thank you very much in advance

       

      Ivan

        • 1. Re: 440MHz in PLL Out Clock is not possible. Denebola Kit
          KandlaguntaR_36

          Ivan,

           

          Can you please provide the full screen short instead only MIPI part?

          I would like to know what is the input data format to MIPI-CSI2 receiver.

          • 2. Re: 440MHz in PLL Out Clock is not possible. Denebola Kit
            IvPe_4204671

            Dear Kandlaguntar,

            Thank you very much for asnwer.

             

            It is my first time with EZ-USB Suite and CX3. After reading the documentation, it is not clear for me if the PLL Out Clock must match the CSI Clock of 440MHz or the default configuration showed is enough. Please, see attached files: "Default Config.PNG" is the default configuration sugested by the tool after entering the Image Sensor Configuration data in the first tab. The second attachment, "After Manipulation.PNG" is a modified version of the same situation, now achieving successfuly the 440MHz previously wished by setting the Pre Divider Value and the Multiplier of Unit Clk field.

             

            However, as I said before, I am afraid I am wrong and the 440MHz are not needed to be equal the CSI Clock.

            In either situation, I have "errors" as you can see in the sceen capture in the Output Pixel Clock (MHz), in the FIFO Delay Time, etc.

            After Manipulation.PNGDefault Config.PNG

            Can you give me a piece of advice?

            Thank you very much for your support

            • 3. Re: 440MHz in PLL Out Clock is not possible. Denebola Kit
              KandlaguntaR_36

              Ivan,

               

              The maximum bandwidth supported by the CX3 MIPI is 2.4 Gbps.

               

              You should make sure that the throughput does not exceed 2.4 Gbps. The throughput can be determined by the formula given below.

               

              Image throughput = bits per pixel × (Horizontal resolution + Horizontal blanking) × (Vertical resolution + vertical blanking) × frames per second

               

              As per your inputs, the image throughput is 3.5 Gbps.

               

              Can you please reduce the fps to 10 (< 2.4 Gbps) and check?

               

              Note:

               

              ---- You have to use output data format as 24-bit instead 8 bit. i.e GPIF II will sample 24-bit per parallel clock.

                    Hence, I changed output format to 24-bit instead RAW8.


              ---- When you set parallel output data format as 24 bit, the Horizontal line bandwidth() should be multiple of 3 bytes. Hence I changed HActive to 4209 instead 4208.

               

              Here is the screen shot of MIPI parameters (ignore the red marks). These red makrs are due to a bug in the tool. We are fixing it in the next revision. As of now, you can use the MIPI configuration as below (for 10 fps).

               

              MIPI Configuartion:

              CyU3PMipicsiCfg_t null_RAW8_RAW8 = 

              {

                  CY_U3P_CSI_DF_RGB888,  /* CyU3PMipicsiDataFormat_t dataFormat */

                  4,                          /* uint8_t numDataLanes */

                  2, /* uint8_t pllPrd */

                  123, /* uint16_t pllFbd */

                  CY_U3P_CSI_PLL_FRS_250_500M, /* CyU3PMipicsiPllClkFrs_t pllFrs */ 

                  CY_U3P_CSI_PLL_CLK_DIV_4, /* CyU3PMipicsiPllClkDiv_t csiRxClkDiv */

                  CY_U3P_CSI_PLL_CLK_DIV_4, /* CyU3PMipicsiPllClkDiv_t parClkDiv */

                  0,                 /* uint16_t mClkCtl */

                  CY_U3P_CSI_PLL_CLK_DIV_2, /* CyU3PMipicsiPllClkDiv_t mClkRefDiv */

                  4209,         /* uint16_t hResolution */

                  0                         /* uint16_t fifoDelay */

              };

              • 4. Re: 440MHz in PLL Out Clock is not possible. Denebola Kit
                IvPe_4204671

                As I already knew about the 2.4Gbps bandwidth limitation in the CX3 documentation, I had reduced the fps from 30fps to 15fps by following the AR1335 datasheet receipt. Such a receipt is based on incrementing the H-Blanking and V-Blanking to control the fps. Then, I was convinced that the Bandwidth was not affected by the total H-Pixels and V-Lines but only for the H-Active and V-Active. Seen this, I conclude: if I follow your indication of reducing to 10fps and I do it by following the AR1335 receipt (by incrementing even more the H and V Blanking), I am afraid I won’t solve the problem.

                 

                There is an alternative and it is by reconfiguring the AR1335 PLL in order to reduce the 440MHz per lane to 294.86MHz so that we will get 589.7Mbps instead of the current 880Mbps. If I do that, I get 20fps and the formula you sent would be: as you indicated:

                Image throughput = bits per pixel × (Horizontal resolution + Horizontal blanking) × (Vertical resolution + vertical blanking) × frames per second

                1. 2.358 Gbps = 8 x (4208 +  448) x (3120 + 30) x 20.1

                Do you think this is a good approach?

                 

                Regarding the 24-bit instead of 8-bit of the output data format. Can you clarify why it is mandatory? I just want to learn. I am not able to change it only in the CX3 MIPI Interface Configuration (section at the right) because it is grayed. Should I change it in the MIPI CSI2 Inputs (From Image Sensor) or manually in the generated code?

                Should I match 1:1 CSI Clock to PLL Out Clock? Or maybe a submultiple 1:2, or 1:4? I would really appreciate the same example you sent with this new configuration attached

                 

                New configuration.PNG

                • 5. Re: 440MHz in PLL Out Clock is not possible. Denebola Kit
                  KandlaguntaR_36

                  >> 2.358 Gbps = 8 x (4208 +  448) x (3120 + 30) x 20.1

                  >> Do you think this is a good approach?

                   

                  This would be fine.

                   

                  >> Regarding the 24-bit instead of 8-bit of the output data format. Can you clarify why it is mandatory? I just want to learn.

                   

                  The maximum value of output pixel clock (this is clock whic drives the parallel interface of GPIF II) is 100 MHz, if you configure the output parallel ineterface as 8-bit or 16-bit, the MIPI block cannot put the received MIPI data on output parallel bus at the same speed it recieves over MIPI.

                   

                  Therefore, you have to set the parallel output bus to 24-bit.

                   

                   

                  >> I am not able to change it only in the CX3 MIPI Interface Configuration (section at the right) because it is grayed. Should I change it in the MIPI CSI2 Inputs (From Image Sensor) or manually in the generated code?

                   

                  You have to change the output format to 24-bit in MIPI CSI2 inputs (image sensor)

                   

                  Note: When you set parallel output data format as 24 bit, the Horizontal line bandwidth() should be multiple of 3 bytes. Hence I changed HActive to 4209 instead 4208.

                  Here is the MIPI configuration as needed.

                   

                  /* null_RAW8_Resolution0 :  */

                  CyU3PMipicsiCfg_t null_RAW8_Resolution0 = 

                  {

                      CY_U3P_CSI_DF_RGB888,  /* CyU3PMipicsiDataFormat_t dataFormat */

                      4,                          /* uint8_t numDataLanes */

                      2, /* uint8_t pllPrd */

                      117, /* uint16_t pllFbd */

                      CY_U3P_CSI_PLL_FRS_250_500M, /* CyU3PMipicsiPllClkFrs_t pllFrs */ 

                      CY_U3P_CSI_PLL_CLK_DIV_4, /* CyU3PMipicsiPllClkDiv_t csiRxClkDiv */

                      CY_U3P_CSI_PLL_CLK_DIV_4, /* CyU3PMipicsiPllClkDiv_t parClkDiv */

                      0,                 /* uint16_t mClkCtl */

                      CY_U3P_CSI_PLL_CLK_DIV_2, /* CyU3PMipicsiPllClkDiv_t mClkRefDiv */

                      4209,         /* uint16_t hResolution */

                      0                         /* uint16_t fifoDelay */

                  };

                   

                  • 6. Re: 440MHz in PLL Out Clock is not possible. Denebola Kit
                    IvPe_4204671

                    Dear Kandlaguntar,

                     

                    I am still figthing with the CX3 and AR1335.

                    Just recalling what you indicated, RGB888 (24bits) per pixel so it would be possible to passthrough without overrun, a question arises:

                    - Wouldn't be correct to declare 4209/3 (i.e. 1403) pixels width in the Frame Configuration Wizard? As I am expecting pixels of 24 bits, but in reality my pixels only have 8 bits. So, I would be waiting for 3 pixels to arrive and they would be counted as 1 pixel of 24bits.

                     

                    Please, let me know if I am correct.

                    Thank you very much for your support.

                     

                    Ivan

                    • 7. Re: 440MHz in PLL Out Clock is not possible. Denebola Kit
                      KandlaguntaR_36

                      Hello Ivan,

                       

                      As per the requirement, if the parallel bus width is 24-bit, the horizontal pixel width should be mupltiple of 24-bits. Otherwise, there will be a timing issue.

                       

                      >> As I am expecting pixels of 24 bits, but in reality my pixels only have 8 bits. So, I would be waiting for 3 pixels to arrive and they would be counted as 1 pixel of 24bits.

                       

                      Yes. It is like something similar as you said.

                      Here the pixel data will be received in chunks and stored in the FIFO and convert it to 24-bit (3 pixels per clock on parallel interface)