I used cyusb314 in slavefifo mode with 16bits bus, and there are two bulk endpoints(0x81 0x01) in it. the dma buffer size corresponding each endpoint is 16*1024 bytes, and the counter of each dma buffer is 2, the pclk is internal(96MHz). The fpga drive the slavefifo bus in negedge pclk. There ar some srange problems about the slavefifo mode.
(1) While I transfer data from fpga to cyusb3014(in diection), the slwr should be last 8193 pclk cycles(in word), then the transfered data are right. If the slwr last 8192 pclk cycles, the data still be right(the counter of in dma buffer must be 2), but if i changed the the counter of in dma buffer like 4, the cyusb3014 will be disconnect when i transfer data from fpga to cyusb3014. you can see the sequence diagram in fig1 and fig2(the slwr last 8193 pclk cycles, and the 4 counter of in dma buffer is ok).
(2) While I transfer data from cyusb3014 to fpga, the transfered datas are correct. if the transfered datas are no more than 256(in word), the data will be transfered only once, the flagc will be 1, and then i can capture the sequence diagram like fig3, but if transfered datas more than 256(like 4096 word), the data must be transfered twice, then the flagc will be 1, and the sequence diagram will be captured like fig4 ,fig5 and fig6, and you can see the counter of captured datas is 8192(in word), why?
(3) In out direction, while the sloe and slrd are 0 after the counter of 1(fig4), the vaild data will be read at the counter 6(posedge pclk), the pdf of cyusb3014 points that the delay of sloe(slrd) and the bus data is 2 pclk cycles, while i find that the delay in my design is 3( the bus data at the counter 2 3 4 is 0), why?
(4) I used some gpio pins in the firmware to control fpga, while i find that the enumeration time of cyusb3014 is too long(it looks like 8-9 seconds), if the firmware is programed in 24AA1025. Is that normal? you can see my firmware in appendix.
SlaveFifoSync.rar 1.4 MB