The default state of GPIOs during different Boots is mentioned in Table 31 of the following document.
Please check if the same state is being retained after Boot. Can you please let me know which Boot option do you use? What is the state of the GPIO 50 and 52 that you see after boot? How do you confirm it is not tri-stated?
FX3 and xilinx FPGA are connected following the suggestion of AN84868 "Configuring an FPGA Over USB Using Cypress EZ-USB FX3
". GPIO 50 are used for FPGA's "done" signal. GPIO 52 are used for FPGA INIT_B signal.
AN84868 is more difficult. Currently, I do not download firmware of AN84868, but rather AN65947, Slave FIFO application. I download firmware to EEPROM and boot FX3 in I2C->USB mode. After wait for enough time (at least 10 seconds), I begin to configure FPGA in JTAG mode but I fail. I observe The GPIO 52 (Init_b) keeps at high level and GPIO 50 (done) keeps at low level. This is why the JTAG configuration fails. I remove the series resistor the route of GPIO52 to INIT_B and GPIO 50 to Done. Then I succeed in JTAG configuration. I observe FPGA's INIT_B present a low pulse after FPGA receives the configuration command by JTAG. The FPGA's Done pin shows high level after configuration,
I read Table 31 of the booting option document and confirmed GPIO52 and GPIO 50 should be tristated before and during booting.
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As mentioned in the thread The GPIO state when FX3 is loading firmware.
Can you please change the GPIO state using CyU3PGpioSetSimpleConfig() to solve your problem?