5 Replies Latest reply on Jul 4, 2019 3:20 AM by HemanthR_06

    CYUSB3014 and Lattice ECP5 Flash selection




      I'm designing a new board with CYUSB3014 and a Lattice FPGA - ECP5 (I have the Lattice VIP EVK that I base my design on it).


      My goal is to program the ECP5 flash via the CYUSB3014.


      I have 3 questions:


           1. is Macronix MX25L3233FZNI-08G flash memory compatible with the CYUSB3014?

           2. How do i connect my SPI channel both the the ECP5 for programming and for the flash memory?

           3. Can I use the same memory for both?




        • 1. Re: CYUSB3014 and Lattice ECP5 Flash selection

          Hi Ofer,


          1. Please refer to the below link for the SPI compatibility:

          Selection of SPI Flash Compatible with FX3/CX3/FX3S/FX2G2/SD3/SD2 and the Recommended Cypress SPI Flash Parts - KBA221833

          2. In your firmware, you can use SSN as software controlled (by using spiConfig.ssnCtrl parameter of SPI config), so that, while accessing ECP5 to program, you can use a GPIO as SSN instead of FX3's SSN pin. If you are performing SPI boot, the SSN line should be connected to SPI Flash on start-up. Then once your firmware boots, as mentioned you can make SPI SSN - Software controlled.

          Let me know if it is not clear.

          3. Do you mean, can the same SPI Flash stores the FX3 firmware image as well as ECP5 image? If that is the question, then yes, it is possible to use the same memory BUT you will have to make sure that you use the Flash area which is available after FX3's image. The image of the FX3 should be present starting from the beginning address of the Flash that is from address zero.




          • 2. Re: CYUSB3014 and Lattice ECP5 Flash selection

            Hi Hemanth thank you for your replay.


            Do you have a block diagram or a schematics reference design for connecting the Fx3 with the ECP5 for programming. I saw somewhere that I need to connect IO's from the Fx3 to the ECP5 jtag pins and not the the SPI pins of the ECP5. Plus if you have a sample code for it it would be great.


            All the best,


            • 3. Re: CYUSB3014 and Lattice ECP5 Flash selection

              Edited: Changed the first line.




              You can NOT program the ECP5 via thorugh FX3 using via JTAG interface of ECP5.


              But, you can do program the ECP5 through FX3 via SPI.


              You can use single SPI Flash for both FX3 and ECP5 firmware.

              Use first half fof SPI flash for FX3 firmware, rest half for ECP5 firmware/register settings.


              Modify the FX3 firmware such away that it reads the ECP5 firmware and writes to ECP5 vis SPI lines. For this purpose, you should use diffferent Select lines for SPI Flash and ECP5 (you can use one GPIO for ECP5).


              On bootup, FX3 loads its firmware. Then it reads the firmware of ECP5 from the SPI Flash and write to ECP5.

              Simple block diagram looks as follows.





              • 4. Re: CYUSB3014 and Lattice ECP5 Flash selection

                Hi Sridhar,


                Thank you for your reply.


                Do you have a code example for the Fx3 on how to do it?


                All the best,


                • 5. Re: CYUSB3014 and Lattice ECP5 Flash selection

                  Hi Ofer,


                  For schematic reference of the above Block Diagram, please refer to the schematic attached in the below link:



                  Regarding the code:

                  Please refer to the following example of FX3 SDK:

                  C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\serialif_examples\cyfxusbspiregmode


                  In this example:

                  1. In the function CyFxSpiInit():

                  The spiConfig.ssnCtrl is made as CY_U3P_SPI_SSN_CTRL_FW. This means that the SSN line can be driven by the software whenever required.

                  Polarity - active low - spiConfig.ssnPol     = CyFalse;


                  2. In the function CyFxSpiTransfer():

                  In the following 'if':

                  - if (isRead)


                  You can see that the statement CyU3PSpiSetSsnLine (CyFalse); will make the SSN line low(in this case the pin C1) - since the polarity is active low.

                  Now, after receiving data using CyU3PSpiReceiveWords() API, we de-assert the SSN by calling CyU3PSpiSetSsnLine (CyTrue);


                  So, what I was telling is:

                  1. Configure one more Simple GPIO as SSN line to FPGA's SPI

                  2. Whenever you want to make a transfer to FPGA's SPI, you can do as below:

                      a. Drive the GPIO low using CyU3PGpioSetValue(GPIO_NUMBER, CyFalse)

                      b. Send/Receive SPI data

                      c. Drive the GPIO high using CyU3PGpioSetValue(GPIO_NUMBER, CyTrue)


                  Even here I am assuming that the SSN polarity is active low.