1 2 Previous Next 15 Replies Latest reply on Jul 15, 2019 9:34 AM by BushraH_91

    simulation result without s25fs128s  timing information

    weshc_4277131

      we using the Flexspi to access s25fs128s model and using read command 0x3. but the model i/o signal without timing information even I load the SDF file _verilog.sdf. the file is download from cypress website. currently, The model (s25fl128s.v) is add in my top testbench and using S25FS128SAGMFI100_F_30pF in the Timings25fl128sModel. and using the $sdf_annotate task to load the SDF file. From s25fl128s document I 3.3.2 I using method 1 to generate SDF file because method 2 is for VHDL. so I don't know which step is missing in my simulation.

      the waveform is shown below and this is a model i/o signal. currently, we can't get the correct value from SO. and always get z. so how to let  s25fs128s i/o have timing information?

      Thanks

      flash_issue.PNG

        • 1. Re: simulation result without s25fs128s  timing information
          BushraH_91

          Hello,

          Thank you for contacting Cypress Community Forum. We are currently reviewing the issue and will get to you as soon as we find the resolution.

           

          Have a wonderful day

          Regards,

          Bushra

          • 2. Re: simulation result without s25fs128s  timing information
            weshc_4277131

            Hi Bushra,

             

            Thanks for your help. can I get resolution in today or tomorrow?

             

            Thanks and Regards,

            WeiShang

            • 3. Re: simulation result without s25fs128s  timing information
              BushraH_91

              Hello WeiShang,

              Unfortunately we need some time to debug the issue. Please bear with me.

               

              Thank you

              Regards,

              Bushra

              • 4. Re: simulation result without s25fs128s  timing information
                BushraH_91

                Hello,

                We do not understand what $sdf_annotate task is doing. The tool you are  using is Synopsys VCS and what needs to be done is back_annotation.  So if the task $sdf_annotate is doing this then the problem might be somewhere else. Can you please elaborate what the $sdf_annotate is doing?

                 

                Thank you

                Regards,

                Bushra

                • 5. Re: simulation result without s25fs128s  timing information
                  weshc_4277131

                  Hi Bushra,

                   

                  we running $sdf_annotate ( `"`WORKAREA/verif_uvm_soc/testbench/modules_v/s25fs128s.sdf`" , testbench.sfm_model,, `"`VSOC_LOG_DIR/s25fs128s.log`" , "TYPICAL"); in my testbench.

                  $sdf_annotate System Task Syntax

                  $sdf_annotate ( “sdf_file” {, module_instance} {, “config_file”}

                  {, “log_file”} {, “mtm_spec”}

                  {, “scale_factors”} {, “scale_type”} );

                   

                  Standard Delay Format Annotation Process

                  1. A Verilog family tool responds to the $sdf_annotate system task, which calls the SDF Annotator.

                  2. The SDF Annotator then reads the configuration file, if one exists. The configuration file

                  filters timing data before it is annotated to a Verilog Family tool.

                  3. The SDF Annotator reads the timing data from the SDF file, which is an ASCII text file that stores the timing data generated by the Verilog family tool.

                  4. The SDF Annotator processes the timing data according to the configuration file commands or the SDF Annotator’s settings.

                  5. The processed data is annotated to the Verilog family tool.

                   

                  Thanks

                  Weishang

                  • 6. Re: simulation result without s25fs128s  timing information
                    weshc_4277131

                    Hi Bushra,

                     

                    1. Do you have VERILOG base testbench can provide us to do the simulation? because we don't have experience in VHDL and cypress website only provide VHDL testbench.

                    2. how to fix the error that is reported from VHDL compiler the FMF library not mapped to a host directory? The error message is shown as bellow. compiler command is  "vhdlan  testbench_s25fs128s_verilog.vhd".

                     

                    Parsing design file 'testbench_s25fs128s_verilog.vhd'

                     

                     

                    Error-[XSYMTABNOLIBMAP] Missing library map

                      Library logical name 'FMF' is not mapped to a host directory.

                      The show_setup command shows all of the mappings for the libraries.  Please

                      use this command to validate that the named library above is mapped to a

                      physical directory in your synopsys_sim.setup file.

                     

                     

                    Thanks

                    • 7. Re: simulation result without s25fs128s  timing information
                      BushraH_91

                      Hello,

                      The question of back annotating the SDF (Standard Delay Format) is probably a question for Synopsys support. Our experience shows that each tool set, and we have tried Cadence and Mentor, have a log info which shows success rate of back annotation. After this if there is an error or miss-format of the SDF suitable error would be printed.

                      Can you confirm that back annotation is done successfully, or simply not sure if the annotation has been done or not?

                      NOTE: The back annotation is done to an instance name. Is your customer using correct instance name? If not then .sdf <INSTANCE> name should be fixed. I also see that they are generating log. What does the log say?

                       

                      Thank you

                      Regards,

                      Bushra

                      • 8. Re: simulation result without s25fs128s  timing information
                        weshc_4277131

                        Hi Bushra,

                         

                        1. The log message is shown below. the Warning show "Scaled timing check limit is out of range" is come from s25fs128s_verilog.sdf in line 68. We modify it to  "3500" and get the error and warning free. but still not get timing information after load SDF files. The instances name "sfm_model" in testbench has modified in  SDF file line 15, 88,92 and no instance name error in the log file.

                        2. Do you have to try the Synopsys tool to load cypress SDF file and shows a success rate of back annotation? and see the correct timing in the simulation?

                        3. is possible given me model timing information and I/O waveform and we can manual fill the timing into the model?

                         

                        -  Log message

                          2    ***   $sdf_annotate() version 1.2R

                          3    ***    SDF file: "/verif_uvm_soc/testbench/modules_v/s25fs128s_verilog.sdf"

                          4    ***    Annotation scope: testbench.sfm_model

                          5    ***    SDF Annotator log file: "/verif_uvm_soc/logfiles/s25fs128s.log"

                          6    ***    MTM selection: "TYPICAL"

                          7    ***    No SCALE FACTORS argument specified

                          8    ***    No SCALE TYPE argument specified

                          9    ***    SCALE FACTORS defaulted to "1.0:1.0:1.0":

                        10    ***    SCALE TYPE defaulted to: "FROM_MTM"

                        11    ***    Turnoff delay: "FROM_FILE"

                        12    ***    Approximation (mipd) policy: "MAXIMUM"

                        14    ***    SDF annotation begin: Mon Jun 10 21:35:57 2019

                        17 SDF Info: +pulse_r/100, +pulse_e/100 in effect

                        18

                        19 Warning-[SDFCOM_STCLOR] Scaled TC Limit Out of Range

                        20 verif_uvm_soc/testbench/modules_v/s25fs128s_verilog.sdf, 68

                        21 module: s25fs128s, "instance: testbench.sfm_model"

                        22   SDF Warning: Scaled timing check limit is out of range, setting to 1.

                        25           Total errors: 0

                        26           Total warnings: 1

                        27    ***    SDF annotation completed: Mon Jun 10 21:35:57 2019

                         

                        - s25fs128s_verilog.sdf

                          1 (DELAYFILE

                          2  (SDFVERSION "2.1")

                          3  (DESIGN "testbench")

                          4  (DATE "Fri Feb 08 11:39:21 2013")

                          5  (VENDOR "Free Model Foundry")

                          6  (PROGRAM "SDF timing utility(tm)")

                          7  (VERSION "2.0.3")

                          8  (DIVIDER /)

                          9  (VOLTAGE)

                        10  (PROCESS)

                        11  (TEMPERATURE)

                        12  (TIMESCALE 1ns)

                        13  (CELL

                        14   (CELLTYPE "s25fs128s")

                        15   (INSTANCE sfm_model)

                        16 (DELAY (ABSOLUTE

                        17     (COND  rd_slow && ~glitch          (IOPATH SCK SO (4:5:6) (4:5:6) (1) (4:5:6) (1) (4:5:6)))

                        18     (COND  (ddr || rd_fast) && ~glitch (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))

                        19

                        20     (COND  dual && ~glitch (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))

                        21

                        22     (COND  QUAD && ~CSNeg && ~glitch (IOPATH SCK RESETNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))

                        23     (COND  QUAD && ~glitch           (IOPATH SCK WPNeg    (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))

                        24

                        25     (COND CSNeg && ~rst_quad (IOPATH CSNeg SO   () () (5.4:6.7:8) () (5.4:6.7:8) ()))

                        26     (COND CSNeg &&  rst_quad (IOPATH CSNeg SO   () () (12:16:20)  () (12:16:20)  ()))

                        27

                        28     (COND CSNeg && dual && ~rst_quad (IOPATH CSNeg SI   () () (5.4:6.7:8) () (5.4:6.7:8) ()))

                        29     (COND CSNeg && dual &&  rst_quad (IOPATH CSNeg SI   () () (12:16:20)  () (12:16:20)  ()))

                        30

                        31     (COND CSNeg && ~rst_quad (IOPATH CSNeg RESETNeg  () () (5.4:6.7:8) () (5.4:6.7:8) ()))

                        32     (COND CSNeg &&  rst_quad (IOPATH CSNeg RESETNeg  () () (12:16:20)  () (12:16:20)  ()))

                        33

                        34     (COND CSNeg && ~rst_quad (IOPATH CSNeg WPNeg  () () (5.4:6.7:8) () (5.4:6.7:8) ()))

                        35     (COND CSNeg &&  rst_quad (IOPATH CSNeg WPNeg  () () (12:16:20)  () (12:16:20)  ()))

                        36   ))

                        37   (TIMINGCHECK

                        38     (SETUP CSNeg SCK (2))

                        39     (SETUP SI       (COND sdro_io1      (posedge SCK)) (2))

                        40     (SETUP SI       (COND ddro_io1      (posedge SCK)) (1.5))

                        41     (SETUP SI       (COND ddro_io1      (negedge SCK)) (1.5))

                        42     (SETUP SO       (COND sdro_quad_io0 (posedge SCK)) (2))

                        43     (SETUP SO       (COND ddro_quad_io0 (posedge SCK)) (1.5))

                        44     (SETUP SO       (COND ddro_quad_io0 (negedge SCK)) (1.5))

                        45     (SETUP WPNeg    (COND sdro_quad_io2 (posedge SCK)) (2))

                        46     (SETUP WPNeg    (COND ddro_quad_io2 (posedge SCK)) (1.5))

                        47     (SETUP WPNeg    (COND ddro_quad_io2 (negedge SCK)) (1.5))

                        48     (SETUP RESETNeg (COND sdro_quad_io3 (posedge SCK)) (2))

                        49     (SETUP RESETNeg (COND ddro_quad_io3 (posedge SCK)) (1.5))

                        50     (SETUP RESETNeg (COND ddro_quad_io3 (negedge SCK)) (1.5))

                        51     (SETUP WPNeg    (COND wr_prot       (negedge CSNeg)) (20))

                        52     (SETUP RESETNeg (COND rst_not_quad  CSNeg) (50))

                        53

                        54     (HOLD CSNeg SCK (3))

                        55     (HOLD SI        (COND sdro_io1      (posedge SCK)) (3))

                        56     (HOLD SI        (COND ddro_io1      (posedge SCK)) (1.5))

                        57     (HOLD SI        (COND ddro_io1      (negedge SCK)) (1.5))

                        58     (HOLD SO        (COND sdro_quad_io0 (posedge SCK)) (3))

                        59     (HOLD SO        (COND ddro_quad_io0 (posedge SCK)) (1.5))

                        60     (HOLD SO        (COND ddro_quad_io0 (negedge SCK)) (1.5))

                        61     (HOLD WPNeg     (COND sdro_quad_io2 (posedge SCK)) (3))

                        62     (HOLD WPNeg     (COND ddro_quad_io2 (posedge SCK)) (1.5))

                        63     (HOLD WPNeg     (COND ddro_quad_io2 (negedge SCK)) (1.5))

                        64     (HOLD RESETNeg  (COND sdro_quad_io3 (posedge SCK)) (3))

                        65     (HOLD RESETNeg  (COND ddro_quad_io3 (posedge SCK)) (1.5))

                        66     (HOLD RESETNeg  (COND ddro_quad_io3 (negedge SCK)) (1.5))

                        67     (HOLD WPNeg     (COND wr_prot       (posedge CSNeg)) (100))

                        68     (HOLD CSNeg     (COND reset_act     (negedge RESETNeg)) (35000))

                        69

                        70     (WIDTH  (COND  rd        (posedge SCK))  (10))

                        71     (WIDTH  (COND  rd        (negedge SCK))  (10))

                        72     (WIDTH  (COND  fast_rd   (negedge SCK))  (3.75))

                        73     (WIDTH  (COND  fast_rd   (posedge SCK))  (3.75))

                        74     (WIDTH  (COND  ddrd      (posedge SCK))  (6.25))

                        75     (WIDTH  (COND  ddrd      (negedge SCK))  (6.25))

                        76     (WIDTH  (COND  RD_EQU_1  (posedge CSNeg))  (10))

                        77     (WIDTH  (COND  QRD_EQU_1 (posedge CSNeg))  (20))

                        78     (WIDTH  (COND  RD_EQU_0  (posedge CSNeg))  (50))

                        79     (WIDTH  (COND  reset_act (negedge RESETNeg)) (200))

                        80     (WIDTH  (COND  reset_act (posedge RESETNeg)) (50))

                        81

                        82     (PERIOD (COND rd SCK) (20))

                        83     (PERIOD (COND fast_rd SCK) (7.52))

                        84     (PERIOD (COND ddrd SCK) (12.5))

                        85   ))

                        86  (CELL

                        87   (CELLTYPE "BUFFER")

                        88   (INSTANCE sfm_model/BUF_DOutZ)

                        89   (DELAY (ABSOLUTE (DEVICE OUT (1)))))

                        90  (CELL

                        91   (CELLTYPE "BUFFER")

                        92   (INSTANCE sfm_model/BUF_DOut)

                        93   (DELAY (ABSOLUTE (DEVICE OUT (1.5:4:6.5))))

                        94  )

                        95 )

                         

                        - instance name in my testbench

                        1374 s25fs128s sfm_model(

                        1375     .SCK     ( dut_io_connections_tb_XSPI_SCK     ),

                        1376     .CSNeg   ( dut_io_connections_tb_XSPI_CS0_B   ),

                        1377     .SI      ( dut_io_connections_tb_XSPI_DATA0   ),

                        1378     .SO      ( dut_io_connections_tb_XSPI_DATA1   ),

                        1379     .WPNeg   ( !dut_io_connections_tb_XSPI_DATA2   ),

                        1380     .RESETNeg( tbw_HRESET_B                       )

                        1381     //.SIO3 ( dut_io_connections_tb_XSPI_DATA3 )

                        1382 );

                         

                        Thanks

                         

                        WeiShang

                        • 9. Re: simulation result without s25fs128s  timing information
                          weshc_4277131

                          Hi Bushra,

                           

                          Do you have a chance to provide new SDF for me? And it can load from $sdf_annotate tool. Currently, we don't have instances name error but we have SDF Warning in "Scaled timing check limit is out of range". 

                           

                           

                          Thanks for your help

                           

                          WeiShang

                          • 10. Re: simulation result without s25fs128s  timing information
                            AlbertB_56

                            Hello,

                             

                            Please find attached the response from the SSE Team :

                             

                            *************************************************************************************

                            We are not sure why you see this.  Are you using a timescale of 1ps/1ps?

                            *************************************************************************************

                             

                             

                            Best regards,

                            Albert

                            • 11. Re: simulation result without s25fs128s  timing information
                              AlbertB_56

                              Hello,

                               

                              Is it also possible to coordinate a "Zoom" meeting with to further discuss this issue?

                               

                              Please advise...

                               

                               

                              Best regards,

                              Albert

                              • 12. Re: simulation result without s25fs128s  timing information
                                weshc_4277131

                                Hi Albert,

                                 

                                Yes, the model using a timescale of 1ps/1ps. So can you provide model and SDF for me and I can try first? If still have a problem then we can have a call with you.

                                 

                                 

                                Thanks for your help

                                 

                                WeiShang

                                • 13. Re: simulation result without s25fs128s  timing information
                                  weshc_4277131

                                  Hi Albert,

                                   

                                   

                                  When be possible have a call with you to discuss this issue?

                                   

                                   

                                  Thanks

                                   

                                  Sean

                                  • 14. Re: simulation result without s25fs128s  timing information
                                    BushraH_91

                                    Hello,

                                    The Verilog model and sdf are provided with the download. We do not have a new model/sdf. Regarding Zoom meeting I will check with model group.

                                     

                                    Thank you

                                    Regards,

                                    Bushra

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