2 Replies Latest reply on May 30, 2019 7:48 PM by cwchc_3277416 Branched from an earlier discussion.

    HX2VL - Individual mode (pin 39) might not meet input low voltage requirement at worst case

    madhul_36

      ‘Input leakage current’ is the current flowing to the chip I/O, when the corresponding I/O configured as input mode.

      This current will draw from external supply; or from another chip’s output connected to it.

      The leakage current will not flow through the pull-down resistor.

       

      Pull-down resistor will not draw current, as the pin is in input mode. The IC pins shall drive in output mode only.

      Since the pin in input mode, and not drawing current, this pin value to be read as near zero.

      If you have a DVK, you can identify this resistor, and take measurement at pull-down resistor. I am sure it will be close to 0V.

        • 1. Re: HX2VL - Individual mode (pin 39) might not meet input low voltage requirement at worst case
          cwchc_3277416

          Dear Madhu,

           

          Please see my comments to your replies below.

           

          There is definitely some leakage current flow through the pull-down

          resistor tied to Gang pin (Please refer to my comment 3 below about Ohm's

          law).

           

          I have only one question to Cypress: please provide an Absolute Value of

          what would be the Maximum leakage current flowing through the GANG pin at

          Worst Case that Cypress guarantee?

           

           

          Just sidetrack a bit: The SELFPWR pin is pulled-up to 5V with 510 kR

          resistor in DVK. This pin fulfills all you definition about leakage

          current: "it is the current flowing to the chip I/O" & "the current will

          draw from external supply".

           

          The same one question: what would be the Maximum leakage current flowing

          through the SELFPWR pin at Worst Case that Cypress guarantee?

           

           

          Thanks & Regards

          Cheok

           

          p/s: I have amended the title to "Individual mode (pin 39) might not meet

          input low voltage requirement at Worst Case to make my question clearer.

          • 2. Re: HX2VL - Individual mode (pin 39) might not meet input low voltage requirement at worst case
            cwchc_3277416

            Dear Madhu,

             

            Cypress data sheet specified -10uA (min) to +10uA (max) of leakage current.

             

            1) "The leakage current will not flow through the pull-down resistor." is incorrect.

            - If "Pull-down resistor will not draw current, as the pin is in input mode." as mentioned by you, then pull-down resistor is not needed (the input pin can be left open) as the voltage at pin 39 will always be absolute 0V (ohm's law 0A x ∞Ω = 0V).

             

            - If +10uA is the leakage current flow from external supply in to CY7C65632

            then -10uA is the leakage current flow out from CY7C65632

             

             

            2) "If you have a DVK, you can identify this resistor, and take measurement at pull-down resistor. I am sure it will be close to 0V." is not addressing the worst case condition (±10 uA) specified and guaranteed by Cypress.

            - If Cypress specified ±10 uA as your limit for leakage current, any IC measured as 10uA leakage current can be shipped from your production.

             

            It is therefore impossible to meet all these specification at the worst case condition:

                 page 17/29: Pull-down resistor of greater than 100K is needed for Individual mode

                 page 19/29: Input low voltage 0.8V (max)

                 page 19/29: Input leakage current -10uA (min) to +10uA (max)

                      10uA x 100kR = 1V, which is over the maximum limit of Input low voltage at WORST CASE

            One of these 3 specifications should be revised to guarantee proper operation at worst case condition.