I Built the one project , It have capsense, I2c , UART, timer blocks but i found the one warning like setup timing violation of cyHFclk.
please tell me how to avoid this warning. (should i worried about it?)
Timing details attached with this case.
General rule: To UDB based component, the maximum clock frequency should not exceeds half of the HFCLK frequency.
If want to pursue maximum UART data rate, i recommend you decrease HFCLK freq to lower speed like 45MHz to avoid the timing error.