I downloaded your project and looked at your TopDesign. I've looked at your pics as well.
I think the problem you might be having is that effectively you've created a logic circuit with an inverter output feed back into the input with some slight delays due to the RC, the comparator propagation delay and the SR register. This configuration by its very nature is a self-oscillating circuit. See the diagram below.
The reason either using a slower clock to the Comparator and/or the SR reg or slowing the response time of the comparator allows the feedback to limit the self-oscillation effect.
Without knowing what you're intending, I can't help much further. (It's not obvious from your code in main().)
Thank you for taking the time to review.
The design supplied is part of a larger circuit meant to decode a signal using hardware only and little or no logic in the firmware. The main() routine is just a driver to produce the signal that the circuit feeds off of.
The comparator/RC/SR are used together to determine the appropriate time in the signal to sample and determine a high/low bit. Once the sample is taken, the capacitor is recharged. The RC is selected to ensure this sample and reset operation is initiated by a rising edge of the signal, and a sample taken at an appropriate time in the signal.
I was hoping to use the fast mode to keep the pulse (used as a clock to the shift register) as small as possible. When running in slow mode or with a reduced clock speed, this can climb up half a microsecond or more. In fast mode the pulse is much narrower, but I run into the issues of self-oscillation as you've mentioned.
Attempting to understand if there is a way to maintain the narrow pulse from the comparator.
Generally I try to stay away from using R, C or L s as timing references unless absolutely necessary.
I still don't understand the need for the RC circuit. Can't it be done with a timer that uses a very good clock source as the input clock?
A word to the wise: Avoid using analog components in a timing chain unless you expect one of the values of the analog components to change during operation and this is a crucial factor in the application. A good example of analog components in a timing chain is the cap sensor. It depends on external capacitance change to increase or decrease the timing.
I fully understand the desire to minimize SW intervention. I always try to use HW state machines to minimize the CPU and boost performance and reliability.
From your TopDesign and your description above, the EdgeDetect1 is used to start the SR reg and the timing for the FET/RC/Comparator chain. This in turn produces a delayed clock pulse for the clock input of the ShiftReg.
Let me propose a change to your circuit in TopDesign. This uses only digital elements in the timing delay for the ShiftReg clock. It also removes the need for the R and C as external connections.
This change replaces your RC, SR, and Comparator and NOT gate with a 16bit Fixed function Counter. The tc output of the counter will provide a rising edge for the shift reg input clock when the count gets to period count value. Since your R (=12K) and C (=3nF) your RC value is 36 usecs. With an input clock to the counter of 24MHz, you need about a period count of 864 to achieve a 36 usec delay from the first edge of the EdgeDetect1 output. You can more accurately control the delay (with IMO = 3MHz: better than +/- 1%). Additionally you can 'tune' the delay value without having to change R or C.
Have tried the alternate solution and it does work for this. The second RC circuit (not pictured) is used to detect both end of data and complete end of message. The protocol repeats the same data stream twice to verify the data has been received correctly across a noisy line. Where I had a single RC circuit for the second function that made a decision based off two voltage levels, it would seem in this case I would use two additional counters to simulate the same logic. Very much appreciated.
My curiosity still wonders if there was a way to eliminate the self-oscillation in comparator fast mode without adding other components on the psoc design such as a debouncer.
If you must use analog RCs in the timing logic, consider using non-inverted logic. You logic has a feedback loop that inverts. It's as if the output is directly feed back into the output of a not gate. This is the standard definition of an oscillation circuit.
Suggestion: Instead of having the FET switch Vdd to the RC, have it switch GND instead. This should invert the output to the comparator input.
I do reiterate that replacing the RC logic with counters gives you more precise and controllable logic. If the project you included here is correct, you have plenty of UDB logic elements left.
Thank you for the insight. I'll incorporate the counter based solution.