I would suggest to put a "Sync" component into the cc path to avoid the timing issue.
Thank you Bob,
but this only results in a another warning:
"Warning-1350: Asynchronous path(s) exist from "Clock_1(FFB)" to "Clock_1". See the timing report for details."
I must say that despite these warnings, I can see the right signals on pins DCC_Data and DCC_Clk on my logic analyzer.
I only feel uncomfortable with these warnings, as if they could incur some instabilities.
I also observe that the warnings also depend on routing to pins:
if I add output pins to cc and ov to watch on my LA,
warnings change or some times even vanish.
I guess that this something to do with different
routings of signals leading to different
timing calculations. It even changes when using different pin numbers.
Try to set pins sync settings to single-sinc / double-sinc (input / output tabs).