Please find my answers to your questions in red:
1. In the AN64846, for 2 layer PCB I can read that the top and the bottom layer PCB have a hatch fill of 7 mil trace and 70 mil spacing, connect to the ground.
--> It'd be really helpful if you can point me the page no where you are pointing this out. The recommended hatch pattern is top layer 7 mil width 45 mil spacing. Maybe you're looking at old app note.
2. What spacing size I have to use with the CY8CMBR3xxx ?
--> Please use top layer 7 mil width 45 mil spacing and bottom layer 7 mil width 70 mil spacing.
I can read on the AN 64846,
First layer : sensor and hatch fill 7 mil trace and 70 mil spacing connect to GND
Second layer : only sensor trace
third layer : GND, (without hatch fill)
bottom layer : component, com trace and hatch fill 7 mil trace and 70 mil spacing connect to GND
-->Attached is a screen shot from the AN 64846. This is the recommendation for 4 layer PCB
Top layer - sensor + 7 mil width 45 mil spacing to ground
Second layer - Sensor traces only
Third Layer - 7 mil width 70 mil spacing to ground
Forth layer - 7 mil width 70 mil spacing to ground +PSoC + Other components + Non CapSense traces
I think that you might be referring to any of our old design documents. Please make sure you're referring to our latest and updated design guide. Please use this link below:
https://www.cypress.com/file/41076/download - Doc No: AN 64846 Rev * X
4. Is the 2 layer better for CY8CMBR3116, or there is no different ?
--> It totally depends on no of components in the design, board dimensions and cost. If you're not able to route all the sensors in your 2 layer PCB (space constraint due to the recommendation that capsense lines shouldn't go near communication/ LED lines) , it will be advisable to use 4 layer. Otherwise 2 layer will be enough.