- Please let me know if you tested using the Cypress USB Control Center application.
- When the FPGA is not sending data, what is the state of the data lines?
- When there is no read request from the host, is the PCLK still active?
Hello Srinath S,
When the FPGA is not sending any data a fixed marking value of 0xBAADBEEF is the output of the FPGA's data lines.
for now the PCLK is always active.
I did not test the firmware using Cypress USB Control Center app. because I could not figure it out how to send control request and in receive data from a Bulk in endpoint in the same time. Is there any document in that regards?
- The firmware is such that it samples the DQ[31:0] lines as long as there is PCLK signal. In the example, the clock source is set as internal and so the clock is provided continuously. In your case, since you have mentioned that the clock signal is always present, the FX3 samples the data lines DQ[31:0] throughout. To stop sampling the data, either the GPIO17 pin needs to be pulled HIGH or the PCLK signal must be cut off. This will eliminate the additional unwanted bytes of data being received.
- Since, you have mentioned that FPGA is sending a fixed value of 0xBAADBEEF, the same should be received on the application when there is no active transfer. Kindly, probe the data lines DQ[31:0] and check if this data is being received.
- To understand using the Control Center, please refer to the CyControlCenter.PDF document in the following path after FX3 SDK installation.
C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\doc\SuiteUSB