1 Reply Latest reply on May 23, 2019 11:51 AM by BragadeeshV_41

    Clocks Duty Cycle

    dakn_263916

      In PSOC 5LP TRM there is a register to use either "Single Cycle Pulse Mode" or

      "50% Duty Cycle Mode".

       

      When a clock is dragged onto schematic what mode is the clock using ?

       

      Is this true for PSOC 4 as well ?

       

       

      Regards, Dana.

        • 1. Re: Clocks Duty Cycle
          BragadeeshV_41

          Hi Dana,

           

          In general Single Cycle Pulse Mode is used in peripherals that uses only the rising edge of the clocks for operation. This is more like clock gating for rest of the period of the clock. The default setting when you drag and drop a clock component in PSoC 5 is 50 % duty cycle mode. You can test this by doing the following:

           

          1. Drag a drop clock component to clock component. Configure the divider and build it.

           

          2. Find the register address for your clock CLKDIST_DCFGx_CFG2. The creator would use the name <clock_alias>_CFG2. You can find this in the cyfitter.h file

           

          3. Enter debugging mode and run and see what is there in the CLKDIST_DCFGx_CFG2 register.  Use register TRM to decode.

           

          (or)

           

          3. Go to cyfitter_cfg.c file which would have configured all the register based on DWR settings. You should be able to find the following piece of code in the void ClockSetup(void):

           

          /* Configure Digital Clocks based on settings from Clock DWR */

          CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0), 0x0BB7u);

          CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x19u);

           

          This option (gated/ single cycle pulse or  50 % duty cycle) is not configurable with respect to PSoC 4 device. It is done by design.

           

          Regards,

          Bragadeesh