I recently started working on a project for which I would need to implement two time-interleaved IDAC-s (each IDAC changes its state on every other sample and increases or decreases its current depending on the wanted output state) for generating a higher-frequency sine wave.
DACs are connected to the DAC bus and their ipolarity and strobe inputs should be controlled by hardware (logic).
Implemented logic should calculate the difference between two input samples (current and previous sample) and, depending on the value and sign of that difference, change state of one of the DACs so that the output matches the current sample. On the next sample it will again calculate the difference, but this time it changes the state of the other DAC. Logic should also need to trigger DAC conversion (strobe signal) and control the polarity of the DACs (current source or sink) via their ipolarity input.
I'm having problems with implementing this logic in CY8CKIT-059 PSoC 5LP.
I made 2 separate projects in which I tried to implement all of the needed logic in Verilog, but build fails on Digital Placement with errors:
Unable to pack the design into 24 udbs in Project "interleaving_2level"
Resource limit: Maximum number of PLDs exceeded (max=48, needed=53) in Project "2_subtractors_crossed"
I am not very experienced with Verilog or any other HDL, so I read some documents and reference guides for PSoCs regarding the use of Verilog in building new components, but I can't find a way to shrink and optimize the design so that it could cram into the PSoC.
The projects I attached are not finished. I connected a simple counter so that I could build the project without unconnected net errors. If I manage to get the design to fit, I would need to generate sine wave samples, so probably even more resources would be used.
I attached the minimal bundles of these projects.
Any help would be appreciated.