12 Replies Latest reply on May 24, 2019 3:33 AM by LePo_1062026

    Need help with fitting design into PSoC 5LP

    user_49479

      Hi,

      I recently started working on a project for which I would need to implement two time-interleaved IDAC-s (each IDAC changes its state on every other sample and increases or decreases its current depending on the wanted output state) for generating a higher-frequency sine wave.

      DACs are connected to the DAC bus and their ipolarity and strobe inputs should be controlled by hardware (logic).

       

      Implemented logic should calculate the difference between two input samples (current and previous sample) and, depending on the value and sign of that difference, change state of one of the DACs so that the output matches the current sample. On the next sample it will again calculate the difference, but this time it changes the state of the other DAC. Logic should also need to trigger DAC conversion (strobe signal) and control the polarity of the DACs (current source or sink) via their ipolarity input.

       

      I'm having problems with implementing this logic in CY8CKIT-059 PSoC 5LP.

      I made 2 separate projects in which I tried to implement all of the needed logic in Verilog, but build fails on Digital Placement with errors:

      Unable to pack the design into 24 udbs in Project "interleaving_2level"

      Resource limit: Maximum number of PLDs exceeded (max=48, needed=53) in Project "2_subtractors_crossed"

       

      I am not very experienced with Verilog or any other HDL, so I read some documents and reference guides for PSoCs regarding the use of Verilog in building new components, but I can't find a way to shrink and optimize the design so that it could cram into the PSoC.

       

      The projects I attached are not finished. I connected a simple counter so that I could build the project without unconnected net errors. If I manage to get the design to fit, I would need to generate sine wave samples, so probably even more resources would be used.

       

      I attached the minimal bundles of these projects.

       

      Any help would be appreciated.

        • 1. Re: Need help with fitting design into PSoC 5LP
          BoTa_264741

          tn_49..,

          What are desired specs for sine output: frequency range, frequency resolution, bits depth resolution, THD, V-scale?

          /odissey1

          • 2. Re: Need help with fitting design into PSoC 5LP
            BoTa_264741

            tn_49..,

            The Verilog code is simply too big even without sine lookup table (which itself will consume >50% of PLD space). I don't see how this approach can fit PSoC5 PLD space.

             

            Other things to consider is IDAC high-frequency performance. Do not expect to see 8-bit output at 12MHz scan rate (closer to ~5-bit). With standard approach DDS-(sine lookup table)-VDAC it is possible to get about 1MHz of low-fidelity sine output, which further declines at ~3MHz to about 30% of original amplitude.     

            /odissey1

            Two subtractors_crossed_A.png

            • 3. Re: Need help with fitting design into PSoC 5LP
              user_49479

              Hi odissey1,

              Thank you for the input.

               

              The sine table would need to have at least 16 samples per period and the frequency of the generated sine wave should be as high as possible.

              The clocks that strobe DACs are just placeholders. I didn't want to mess with timing because I wasn't sure if the design is even going to fit on this board. The DACs should be ideally running at their max speed (8MSPS) and the equivalent speed of 2 interleaved DACs should theoretically be double the speed of a single DAC.

               

              Do you think that calculating the delta values beforehand and converting them instead of sine wave samples would be a viable option. This way deltas wouldn't need to be calculated and the sub_logic_1 block wouldn't be needed.

              • 4. Re: Need help with fitting design into PSoC 5LP
                BoTa_264741

                tn49..,

                Attached is example project making approx. 1MHz fixed frequency output sine at 1V p-p amplitude. The output frequency is limited by Opamp slew rate. The THD is in the -35dB range. Above 1MHz, sine quality is sharply decreasing, becoming more like a triangular. As shown, system resources consumption ~11%.

                 

                Project includes several pages (VDAC8 with and w/o Opamp, IDAC8, 32/16point-per-period) to test various modes. Disable current page prior to enabling another one. It demonstrates that limitation is not in the digital, but in analog domain. It all boils down to proper balance of various specs: frequency tunability, range, resolution; amplitude tunability, resolution, V-scale; THD.

                /odissey1

                 

                Sine_01c_sch.png

                Sine_01c_B.png

                Sine_01c_C.png

                • 5. Re: Need help with fitting design into PSoC 5LP
                  LePo_1062026

                  odissey1,

                   

                  You show an optional offset of Vdda/2 as a Vref output attached to the output of the VDAC.  Does that work?  What is the output drive configurations of Vref and VDAC that would allow in effect the equivalent of an analog mixer?  You hit my 'curious' button.

                   

                  Len

                  • 6. Re: Need help with fitting design into PSoC 5LP
                    BoTa_264741

                    Len,

                    Scope traces provided with VRef set to Vdda/2 as shown on the schematic.

                    The VDAC 8 is in strong drive mode, 1.024V scale, impedance 4k. VRef set to Vdda/2 (can use Vdda), impedance 100k(?). So, effectively, it acts as summing junction. The VDAC amplitude drops about 20mV, and shifts up few hundred mV. The Opamp is not rail-to-rail, with compliance voltage somewhere 150 mV above the GND rail, and this pull-up helps to avoid Opamp going into saturation. From the FFT, it seems to lower THD by ~3db.The IDAC8 can be used instead, but VRef is "cheaper".

                     

                    Same approach can be used for providing voltage offset when sampling AC signal through serial capacitor - just add VRef. It seems that the buffered 1.024V has ~20k impedance, so it won't affect AC signal much, and can shift AC to ADC level.

                     

                    We tend to think about analog components as an ideal parts, but it isn't the case in PSoC.

                    /odissey1

                    • 7. Re: Need help with fitting design into PSoC 5LP
                      LePo_1062026

                      odissey1,

                       

                      Thanks for the quick reply!

                       

                      I figured it might be possible with caveats of course.

                       

                      In the operational mode you describe with the Vref, wouldn't other internal Vrefs (such as Vdda and Vdda(Hiz-Z) be effected since Vdda/2 is derived from Vdda?

                       

                      Len

                      • 8. Re: Need help with fitting design into PSoC 5LP
                        BoTa_264741

                        Len,

                        PSoC doesn't allow both Vdda(hiZ) and Vdda/2 at the same time, it is ether one or another. (I didn't check for Vdda though).

                        /odissey1

                        • 9. Re: Need help with fitting design into PSoC 5LP
                          user_49479

                          Hi,

                          sorry if I didn't make it clear, but i should be working with IDACs only.

                           

                          odissey1,

                          I guess that the end goal of the project I'm currently working on is generating sine waves with frequencies exceeding only one DAC's capabilites and without sacrificing the resoultion. Using 2 IDACs (or even adding up to 4 in the future) with appropriate timing and logic should (in theory) result in ability to generate a sine wave with double the frequency of a sine generated with only one DAC, without any sacrifices, apart from increased resource usage.

                          That's why I'm insisting on using IDACs. And again, sorry if I didn't make it clear enough in my original post.

                          Adding external components like opamps with higher slew rates is also an option if built-in opamps aren't good enough.

                          Would you mind if I try to modify your example?

                           

                          Using precalculated delta values kind of works, but I must have miscalculated something because the output periodically starts with a sine wave, but then it starts drifting towards Vdd and clipping and the generated output becomes trash. Since this is more of a workaround and not a solution, I am considering using less of the DACs input range and calculating sine samples delta in logic, but using fewer bits.

                           

                          Thanks,

                          Tomislav

                          • 10. Re: Need help with fitting design into PSoC 5LP
                            BoTa_264741

                            Tomislav,

                            Feel free to use and modify the demo project. It was drafted to demonstrate that DAC sine output reached the "figure of merit" (all specs are stretching). From that point increasing of any parameter will cause another ones only to worsen. For example, increasing frequency to 2 MHz will distort the shape and reduce signal amplitude (about twice).

                             

                            The project supposed to show that the limitation is in analog path (RC), not digital. So I would recommend to test it's limits first.

                             

                            The VDAC8 and IDAC8 is same hardware component, but VDAC has extra load resistor (4k @ 1.02V). So, one can combine outputs IDAC1 + IDAC2,  VDAC1 + VDAC2, or VDAC1 + IDAC2.

                             

                            Anyways, this is interesting approach, please share your project with community if permitted.

                            /odissey1

                            • 11. Re: Need help with fitting design into PSoC 5LP
                              BoTa_264741

                              Tomislav,

                              I drafted a project to test effect of combining 2 and 4 interleaved DACs (attached). The finding is that linear interpolation works at low sampling frequencies (125kHz), reducing sampling clock frequency in FFT by almost 20dB. Unfortunately, at higher frequency (1MHz) it practically has no effect because individual DAC signals are heavily distorted and smoothed by parasitics. External opamp (LT6200) with GBP of 165MHz was used (with only slight improvement, compared to the internal opamps). Using IDAC8 with external load resistor instead of VDAC8 did not improve performance.

                              /odissey1

                               

                              Fig. 1. Outputs of two interleaved VDAC8 are combined for linear interpolation. Clock_1 divider controls sine output frequency.

                              Sine4_01a_scm_A.png

                              Fig. 2. VDAC_0 leads VDAC_1 by (1/2) sample (Pin_30 and Pin_31 are not joined).

                              VDAC_125kHz_2x16_C.png

                              Fig. 3. Signal from a single Pin_30, (Pin_31 is not connected). Clock_1 divider = 16, output frequency 125kHz.

                              VDAC_125kHz_1x16_B1.png

                              Fig. 4. Signal from Pin_30 and Pin_31 combined. Clock_1 divider = 16, output frequency 125kHz.

                              VDAC_125kHz_2x16_A.png

                              Fig. 5. Signal from a single Pin_30, (Pin_31 is not connected). Clock_1 divider = 2, output frequency 1MHz.

                              VDAC_1MHz_1x16_B.png

                              Fig. 6. Signal from Pin_30 and Pin_31 combined. Clock_1 divider = 2, output frequency 1MHz.

                              VDAC_1MHz_2x16_A.png

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                              • 12. Re: Need help with fitting design into PSoC 5LP
                                LePo_1062026

                                \odissey1,

                                 

                                Bravo!   I liked how your approach cleaned up much of the lower harmonics.

                                 

                                Len