8 Replies Latest reply on May 21, 2019 7:02 AM by LePo_1062026

    PSOC capacitive load capabilities

    sozoc_2537926

      Hello, everyone !

       

      This my first post at the community although I've studied a lot on PSOC devices and have seen many interesting posts here.

      My question is the following:

      Let's have a single GPIO pin (Not a SIO one). The datasheet mentions that it can source 4mA and sink 8mA safely.

      Now if I have a long line on a pcb that presents a capacitive load of lets say 200pF. If I want this GPIO pin to drive the line (5V system) I need a 5/0.004 = 1250R total resistance. I know that the internal mosfets driving the pin present a resistance (when sourcing current) of about 40-50R (page 70/122 of CY8C5268AXI-LP047)  then I need an 1K2 external resistance.

      Are those currents, average currents? Because if I drive a 25pF load (as the datasheet mentions as an example of rise/fall times) without an external resistor, the switching current charging the capacitor is going to be 5V/50R =100mA which is a lot??

       

      Unfortunately I can't find anywhere the SOA of output mosfets to have a clear understanding of my concerns....

        • 1. Re: PSOC capacitive load capabilities
          LinglingG_46

          For the capacitance circuit, I=dQ/dt= dCu/dt=C du/dt , at the beginning, if the U=5V, R=50, then the current I should be equal 100mA, but the GPIO only can drive 4mA, so the voltage will be pull down. U=4mA*50=200mv.

          • 2. Re: PSOC capacitive load capabilities
            sozoc_2537926

            If the current is limited to 4mA, which mean a 1K2 effective resitance (5V/1K2 = 4mA) somehow internally then charging a cap with a constant current of 4mA gives rise times close to the pdf value.. But how current is limited to 4mA ???

             

             

            PSOC_PIN_ACresponse.png

            • 3. Re: PSOC capacitive load capabilities
              BoTa_264741

              I don't believe there is a current limiter built into the pin. From personal experience, a pin in strong mode can be loaded directly to about max 10n cap without penalty. Unfortunately, I tested it with larger caps also; using 100n cap as a load blew up the pin on KIT-059 (two of them, to confirm it). Now on startup they show +5V. Another one hits the dust...

              /odissey

              • 4. Re: PSOC capacitive load capabilities
                LinglingG_46

                As my understanding, the current limited by the MOSFET in below figure. More details, you should refer to the JET theory. 

                Because of the MOSFET, the GPIO can't give more than the 4mA (4 mA parameter from chip datasheet)  current at anytime.

                • 5. Re: PSOC capacitive load capabilities
                  BoTa_264741

                  LinglingG,

                  I suspect that in strong mode the top FET is connected to Vdd; once it is open, only the parasitic resistance will limit the current (unless there is a current source on top of the FET). From two blown pins I conclude that it is not safe to short-circuit pin in this mode - there is no guarantee that current will be automatically limited to ~4mA.

                  /odissey1

                  • 6. Re: PSOC capacitive load capabilities
                    LePo_1062026

                    Hi,

                     

                    I'm glad to see people are using another Great tool available: LTSpice!

                     

                    I've worked with FETs before and understand the problem.  The lower the Rdson the FET can provide the higher the input capacitance.  This is because internally the FET is actually paralleling the equivalent of smaller higher Rdson FETs,  They do so by elongating the Drain and Source junction which ends up elongating the Gate.

                     

                    I'm assuming that you are using a "dumb" FET.  By "dumb" I mean the FET IC is just the FET.  "Smart" FETs have many other additional functions which include protection circuits and most importantly a FET gate driver.  The FET gate driver is sized to drive the capacitance of the Gate without having the user worry about it.  To the user, the input impedance can be driven with 1K ohm and the input capacitance is < 12pF.

                     

                    If you're going to use a standard "dumb" FET, you may need a gate driver.  You can construct a gate driver using a NPN/PNP pair such as the NXP PUMD2.

                     

                    The datasheet for the PSoC5LP for Voh = Vddio-0.6V when driving 4mA load @Vddio = 3.3V  Therefore the internal source resistance when driving the digital GPIO pin high is worst-case 0.6V/4mA = 150 ohms.

                     

                    A fully discharged load capacitance (let's pick 25pf) acts like a temporary short.  Therefore the initial surge current when driving the GPIO from 0 to 1 is 5V/150ohms = 33.3mA.   This about 8x times more than rated current.  However, the PSoC is designed to thermally take these surges currents all day.

                    The simulation plot below models the GPIO output with 150 ohm internal resistance a 1MHz pulse at 5V driving 25pF.  The plot is the wattage of the 150 ohm resistance of the high switch (S1) which is the only consuming structure in the PSoC on the 0 ->1 transition.  The single pulse is has an average power of 326uW.  If I increase the number of pulses to 1 Million, (one second of operation)  my average power remains the same.  Since 326uW is about 1000x below 300mW for the device package, not much to worry about.  The PSoC was designed to current surge to 33mA if needed.  Also the instantaneous energy of any single pulse is 326pJ.   I double this value because the power dissipation also includes the 1->0 transition and I'm still  in the "safe-zone".

                    As predicted, the rise time is about 9.3ns.

                     

                    If I increase C1 to 200pF, my rise time is now 66.6ns and my average power dissipation is 2.5mW which is 7.7x more power than with the 25pF cap.  Additionally the energy S1 sees is now 2.5nJoules which is 7.7x higher.  You might be able to get away with the additional average power increase but only Cypress can tell you if the internal instantaneous energy increase may damage the GPIO (S1 and S2).

                     

                    I know I was a bit wordy, but hopefully this might give some insights to the design issue you are facing.

                     

                    In summary, since you are exceeding the 25pF output drive capacitance, consider at least using a NPN/PNP driving pair external to the PSoC to drive the FET gate.

                     

                    Len

                    • 7. Re: PSOC capacitive load capabilities
                      sozoc_2537926

                      First of all thank you guys for all your answers and your time.

                       

                      I tend to agree with "Len" here. I performered experiments with a PSOC5 MCU and some ceramic caps. Driving a 22pF/60pF/330p/1nF cap directly with a small 20R resistor to sense the charging/discharging current and some series resistances. My conclusion is that during charging the initial current is high enough even with a 22pF load. the GPIO 4mA/8mA values (average current) simply guarantees valid logic levels. The pdf mention ~30-40mA source/sink capability of a single pin as an absolute maximum. With just 22pF at the output I got around 15mA max current. So I think that choosing a series resistor to limit the initial current to eg. 20mA is the way to go. So for 5V I need ~250R of total resistance.

                      The internal resistance varies between 50-150R depending on whether you look the graphs(typical values) or the table (maximum/minimum values).

                      • 8. Re: PSOC capacitive load capabilities
                        LePo_1062026

                        Sotiris,

                         

                        I'm glad you got a chance to experiment.  Your experiment data can provide you with good info to create models for any simulations in the future.  I do wish Cypress would publish IBIS model info for their external IO structures.

                         

                        It's always a good idea to place a current limiting resistor in series if possible.  It does three things:

                        1. Limits capacitive surge effects (the basis of this discussion)
                        2. Reduces Vdd and Vss 'bouncing' effects.  This helps to make your bypass caps on the voltage domains smaller and more effective.
                        3. Limits radiated and conducted emissions (important if your customer needs EMC compliance).   The RE and CE emissions are improved by lower the di/dt values of circuits.

                        Your design needs to consider the rise and fall times with a larger series resistor.  This might be a bigger problem in some circuits. 

                         

                        For example: Driving a FET directly can be done with the PSoC.  The FET gate steady-state current can be very small <100uA.  However, because the FET can have very large input capacitance, the input switching currents can be quite large.  Note:  The general rule-of-thumb is that the lower the Rdson for the FET, the larger the input capacitance.

                         

                        The PSoC can drive these larger capacitance directly with a larger series resistor.  The larger resistor will significantly increase the rise and fall times (Rseries * Cin_fet = tau of rise and fall).  The downside is that the FET will be in the linear region of operation longer.  With the FET in the linear region, it will heat up more depending on the load it is driving.  This means that the design needs to account for thermal effects especially if the FET is being used to PWM a load.  The faster the frequency of PWM, the more average power dissipated in the FET.

                         

                        If the FET is being used as an occasional switch that has a very low switching frequency, the design can probably thermal tolerate a direct drive from the PSoC.

                         

                        For this reason, FET manufacturers recommend FET gate drivers to off-load the surging effects and allow for quicker rise and fall times.

                         

                        Len