2 Replies Latest reply on May 15, 2019 5:55 AM by premji.chaudhari_3505471

    how GPIO[27] became master-clock from FX3 to FPGA CCLK pin.

    premji.chaudhari_3505471

      Hi All,

       

      Please go through attached snap which is about GPIF-tool based interface definition for FPGA configuration using slave-select-parallel-map.

      Now if you look at CLK to GPIO[16] that is nothing but schematic-wise it is common 100MHz clock frequency. It is derived from 100 MHz clk-oscillator and sends 100 MHz to both FPGA and FX3 chip.

      Now if you look at FX3 GPIO[27] pin to FPGA CCLK pin which provides clock frequency when FX3 writes FPGA bin file into it.

       

      My worry is that i dont know how this GPIO[27] generated 100 MHz clock frequency ? I went through GPIF design, but no-where found relationship between GPIO[16] and GPIO[27]. Then how it provides 100 MHz clock ? where it is defined or configured to do so ?

       

      Please let me know, it'll be very helpful for me.

       

      Thanks,

      Premji