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      • 15. Re: need help on power supply section of psoc-5lp  for best performance of 20bit adc
        prbhc_3338016

        user_119654 wrote:

         

        quad,

         

        A smps is OK if the smps circuit is not on your PCB.  If it is in a "wall-wart" module with a DC output, the physical distance to your PCB will be most likely enough isolation.  If the smps is very close to your PCB, not so much.

         

        If the smps is a regulated DC output at 12V, then here is a simple low-cost circuit to use to output 5V to the PSoC and downstream circuits.

        The Vreg U_1 can be a very low-cost LDO with a fixed 5.0V output.  Note: most SMD LDOs are about 100mA max output.  With proper thermal design, you can use a 1A version (usually a beefier package) if needed.

         

        The bulk caps C_2 and C_3 are for low-frequency mostly load variances.  C_4 (smaller value but high-frequency lower-impedance) is used to filter possible smps-induced high frequency noise from passing through the Vreg.

         

        Len

        Great explanation  Len sir.

         

        Now i am close to designing the pcb . But last few queries.

        (1) smps is modular pcb which will be inside cabinet of the product a 1.5 inch away from psoc board. now i need to know what protection circuitry is needed to not to harm the 20 bit adc performance .

         

        (2) As per ap note to acheive analog performance digital supply and analog supply regulator should be different and so the grounds aswell.

        Do i need to used two ldos. I am willing to use AMS1117-adj or AMS1117 5v and AMS1117 3.3volt regulators. ALL other components driving higher current will make use of other regulator.  I am thinking that  proper load distribution will keep the thermal heat to minimum as the product will be in plastic cabinet.

         

         

        This post queries will help many others out there to achieve success. As power section if not designed properly can lead to hidden errors.

        • 16. Re: need help on power supply section of psoc-5lp  for best performance of 20bit adc
          LePo_1062026

          quad,

           

          1.5 inches away ... hmm.  Is the smps in a Faraday cage enclosure?  Ie:  Is the smps assembly have a wire mesh surrounding it?

           

          Q1)

          Optimally, it is better to Faraday shield the "offender" (smps) than the one "offended" (your design).  Faraday shields can be simple but it's an added cost everyone wants to avoid.

           

          Given the small distance to your PCB, there are other mitigation techniques but each one will add costs.

          In general, the "low-hangiing-fruit" of mitigation will be a 4-layer PCB.  This should allow the most mitigation with the lowest overall cost of BOM components and manufacturing problems.

           

          Suggestion:  You've already prototyped using your PSoC5-kit.  Try to package all your components as close to production-intent in a prototype housing.  See if your design is prone to RE EMI as is.  If it is, try Faraday shielding on the smps.  If it goes away or improves, the smps is a source of the noise.

           

          Knowing if there is potentially a problem or not, design your production-intent PCB with the best layout practices available in the industry.  This may require some research on the internet or a book resource.

           

          Send this layout to a prototype PCB manufacturer for a quick-turn low-cost run of 5 to 10 PCBs.   Assume if there is a noise issue, you may need more than one revision of the design.  It sucks but it is commonly a reality.   This is because EMI issues can be what I call "Science-Voodoo".  The physics of design is exact (hence the Science part) but the environment it operates in is VERY COMPLEX (hence the Voodoo).  Experienced engineers use as much personal experience as well is outside experts as "lessons learned" to start a design.  Even with this as a good head-start, surprises are not uncommon.  Surprises = Opportunities for new lessons learned.

           

          Q2)

          Be careful when using different LDOs to supply VDDD and VDDA.  This could cause unnecessary issues.  The reason there is a concern when directly connecting VDDD directly to VDDA is that sometimes the high-speed switching currents to clock logic in the digital domain can be seen as supply transients in the analog domain.

           

          Here's a low-cost suggestion:

          Each supply domain is de-coupled with a cap (C_5 and C_6).  These caps MUST BE placed a close to the PSoC pins as physically possible.  There is a 0 ohm resistor is a place-holder for a potential in-line ferrite bead inductor.  As needed, you can replace the 0R with some in-line inductance to minimize VDDD switching influences on VDDA.  If no inductance is needed, a 0 ohm resistor is very low cost.  In this design, it shares 5V for VDDD and VDDA to use only one Vreg.

          Len

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          • 17. Re: need help on power supply section of psoc-5lp  for best performance of 20bit adc
            prbhc_3338016

            Thanks for the reply.

             

            I had already suggested this to the client but now I will make sure to use faraday cage as this is best option.

             

            What if i use two LDO's?.apnote also suggest the same for good analog performance. I think i should separate the analog and digital section. what you suggest.   As I need this thing to be working for demo. Atleast i can try to keep the performance upto the mark . The analog ldo will not add much cost though.

             

             

            Q2)

            Be careful when using different LDOs to supply VDDD and VDDA.  This could cause unnecessary issues.  The reason there is a concern when directly connecting VDDD directly to VDDA is that sometimes the high-speed switching currents to clock logic in the digital domain can be seen as supply transients in the analog domain.

             

            Len

            what unnecessary issue sir?  if i use two ldo's.

            I think problem may arise if i connect and share vddd to vdda.

             

            Also i am thinking to shield the psoc itself .

            • 18. Re: need help on power supply section of psoc-5lp  for best performance of 20bit adc
              LePo_1062026

              quad,

               

              Some of the unnecessary issues are:

              • The Vreg for VDDA is faulted OFF and the CPU (running off VDDD) ASSUMES VDDA is good.  Fix:  Check for VDDA LVD (Low-Voltage Detect) before performing a Analog function.
              • Be careful of analog circuits driven by VDDD power.  There might be a back-feed of current from VDDD especially if VDDA is significantly lower than VDDD or faulted off.
              • Fewer BOM components mean lower MTTF (Mean-Time-To-Failure).
              • A simpler assembly with fewer chances for assembly failure in mass-production.  Also fewer test points.

              It's your call.  My normal "go to" decision is try it from the same Vreg and upgrade to a dual-Vreg design if the results aren't good enough.

               

              Suggestion:  If you're design allows it, construct a layout where you can have 'Protect4' design elements.  You can 'Protect4':

              • two Vreg. (Second Vreg optional)
              • One common Vreg with the filtering shown in an earlier post. (Optional installable filter comps)
              • Attachment points for a Faraday shield. (Optional install)

              One you get the first revision of the PCB, you can start with the simplest, low-cost cost solution [One Vreg with filtering] (this always makes the customer happy).

              You can experiment by adding the second Vreg.  Do you see improvements?

              If needed, you can add the Faraday shield.  Improvements?

               

              Once you have a solid solution, you can either commit the design with that revision of PCB or go through an layout to remove unneeded 'Protect4' components.

               

              Len

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              • 19. Re: need help on power supply section of psoc-5lp  for best performance of 20bit adc
                prbhc_3338016

                Thanks a lot Len and Gill,

                I appreciate the knowledge share to me. I will design the circuitry, develop the pcb and the post the circuits following this topic. So that many new users can take a knowledgeable inputs and learn to built power section.

                • 20. Re: need help on power supply section of psoc-5lp  for best performance of 20bit adc
                  JOLO_264146

                  Hi,

                  as reference fyi. I use this design as core module (for P3 and P5LP). I'have one similar for P1 (with connectors in the same position and with same signals) and I'm finishing other for P62 and P63 (although these last ones are in stand by. I prefer to use P3/P5LP )

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                  • 21. Re: need help on power supply section of psoc-5lp  for best performance of 20bit adc
                    prbhc_3338016

                    p1 psoc1

                    p3and p5 psoc 3 psoc5lp

                    p6 psoc 6 

                    I got it.

                     

                    Refrence design is good.  It would be helpful. Thanks a lot..

                     

                    I am not greedy   but can you share board files. which software is this used for schematic / pcb design

                    • 22. Re: need help on power supply section of psoc-5lp  for best performance of 20bit adc
                      JOLO_264146

                      Hi,

                      I use a "old" version of Orcad (10).

                      Attached the files

                       

                      Regards

                      Gil

                      • 23. Re: need help on power supply section of psoc-5lp  for best performance of 20bit adc
                        prbhc_3338016

                        thank you gil,

                         

                        i have finished the design of pcb yesterday. But the shcematic u shared will help to cross verify . thanks a lot

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