1 Reply Latest reply on May 17, 2019 6:19 AM by HemanthR_06

    fx3 minimum complex gpio PWM period bug




      I am using the EZ USB FX3 board to build an interface to an external device that requires an approx. 100MHz clock and puts out a serial 100MHz serial output data stream.

      In order to make the interface work, I need the FX3 to generate 2 approx. 100MHz output clocks, with adjustable phase difference.

      I use the FX3 PCLK as a master clock running at approx 100MHz. That works fine.

      Now I want to generate a second output clock signal, at the same frequency, but with controllable phase shift w.r.t. PCLK by using an FX3 internal DLL (delay locked loop).

      I managed to generate the 2nd clock signal on a GPIO pin by using complex gpio, in PWM mode, and setting period and duty cycle with period and threshold ticks.

      I am also able to change its phase with respect to the PCLK by using an FX3 DLL.

      However, it seems that PWM period settings smaller than 8 have no effect on the period of the PWM signal. I was not able to get a 100MHz gpio complex output signal,

      also not by decreasing fast clock div value. At best I got approx. 25MHz.

      I found out that this was confirmed in one of the entries in the developer community as a bug in the FX3 chip with PWM period settings smaller than 8.


      I have a few questions:

      - are there (newer) versions of the FX3 where this minimal PWM period bug has been fixed?

      - are there alternative ways, other than complex gpio, that allow for generating 2 100MHz output clocks with adjustable phase relation?

        I did read about the SDIO interface with S0 & S1 ports that talk about the ability to generate 100MHz clocks, and with a seperate DLL, which is "recommended not to use"

        in the technical manual. Is it possible to use these to generate a steady 100MHz clock with adjustable phase, without actually implementing a full SDIO interface?


      Any help is appreciated,

      Best regards