6 Replies Latest reply on Jun 9, 2019 11:36 PM by EktaN_26

    UDB behaviour of Fx_LD and Dx_LD signals

    raal_264636

      Hi,

       

      I want to transfer data from UDB => FIFO => D0/D1 registers. In the 5LP reference manual, the description of the Fx_LD and Dx_LD signals is not clear to me. So I've some questions:

       

      For the Fx_LD signal, I assume it has no effect if FIFO is in input mode (system bus writes the FIFO). Is this true? Or can the FIFO even been loaded from datapath when in input mode?

       

      For the three FIFO output modes, let's say there's a UDB implementation which has five states 1-5.

      1) some UDB computation, Fx_LD signal is set high

      2) no UDB computation, Fx_LD signal is recognized by datapath as rising edge, Fx_LD signal is reset, FIFO is loaded from Ax/ALU, Dx_LD is set

      3) no UDB computation, Dx_LD signal is recognized by datapath as rising edge, Dx_LD signal is reset

      4) some UDB computation with Dx, where Dx has been loaded from FIFO

      5) some UDB computation

       

      Is the above interpretation true? If yes, is it possible to merge states 2 & 3?

      If I understand the description of the _LD signals correctly, the transfer occurs at the falling clock edge. So, using FIFO clock inversion and setting both Fx_LD and Dx_LD in state 1 should make the FIFO recognize the rising edge within state 1. At state 2, the FIFO transfer completed, and Dx_LD will recognize the rising edge.

      In state 4, Dx is loaded from FIFO, so state 3 is eliminated.

       

      How would the FIFO edge/level setting affect the above? If set to level, would it mean that the FIFO is loaded at each falling clock edge on each state where the Fx_LD signal is high on the rising clock edge? So, it would be possible to load the FIFOs with the datapath clock, but the Dx registers can only be loaded at half the clock frequency?

       

      Regards

        • 1. Re: UDB behaviour of Fx_LD and Dx_LD signals
          EktaN_26

          Hello Ralf,

           

          • The FX_LD signal does not have any affect if FIFO is in input mode.
          • FIFO cannot be loaded from datapath in the input mode.

           

          Can you let me know that whether you are tryng to transfer the data from accumulator to FIFO and FIFO to D0/D1 in the same clock cycle?

           

          Regards

          Ekta

          • 2. Re: UDB behaviour of Fx_LD and Dx_LD signals
            raal_264636

            Hi Ekta,

             

            in general, I'm interested in how the Fx_LD/Dx_LD signals works. Transferring Accu/ALU result to FIFO and FIFO to Dx in one cycle is just for interest, currently it seems not neccessary for my goal. But it would be nice to know if it's possible.

            Reason why I ask about the Fx_LD/Dx_LD signals is because I want to chain three UDBs, where one computation value is stored in Dx. Since it's not possible to make atomic CPU Dx access over three UDBs (24-bit), I want to use the FIFO and its block/status signals to achieve the atomic access.

             

            I'm more interested in the internal UDB timings in general. Regarding this, the documentation isn't useful IMO. I find it hard to understand because all the informations are scattered around several pages of the reference manual. Some timing diagrams with the control signal states and their effect would be appreciated.

             

            For example, from the reference manual, how can I figure out how the transfer ALU=>FIFO works? The documentation states that the Ax WrSrc writes the accumulator after(!) the ALU operation completes - but where's stated when it completes? I can only assume that this happens on the UDB falling clock edge. So, from this assumption, I also assume that the ALU keeps its result until the next falling edge, which is why the Fx_LD signal must be activated in the same cycle which computes the result to be transferred. But it's all based on assumptions.

            Can you confirm the above?

             

            Regards

            • 3. Re: UDB behaviour of Fx_LD and Dx_LD signals
              raal_264636

              EktaN_26, are you still following this topic?

               

              Regards

              • 4. Re: UDB behaviour of Fx_LD and Dx_LD signals
                EktaN_26

                Hello Ralf,

                 

                You can have a look at the following:

                C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\sim\presynth\vlg\cy_psoc3_dp.v

                 

                I have attached the verilog file below

                 

                The last para of the file mentions the clocks on which D0 and F0 signal are updated.

                 

                Regards

                Ekta

                • 5. Re: UDB behaviour of Fx_LD and Dx_LD signals
                  raal_264636

                  Hi Ekta,

                   

                  thank you for pointing to this file, interesting. Can this file be used to simulate a UDB/datapath? If yes, does Cypress provide a toolchain for this?

                   

                  Regards

                  • 6. Re: UDB behaviour of Fx_LD and Dx_LD signals
                    EktaN_26

                    Hello Ralf

                     

                    You can use verilog file to simulate UDB/datapath using datapath configuration tool.

                     

                    Please have a look at the example given in following appnote:

                    Designing PSoC Creator component with UDB Datapath: https://www.cypress.com/file/41531/download

                     

                    Regards

                    Ekta