You can verify the numbers against the datasheet values as provided in Table 9 of EZ-PD CCG4 datasheet.
The entry into deepsleep and exit to active depends on the port roles, then as you said, average can be calculated.
The current drawn on Vddd will only depend on GPIO sourcing currents + core power consumption (datasheet).
If you are sourcing VCONN, current will be drawn from V5V_Px supplies.
Thank you for the quick reply. Does that mean that we only have to exit deep sleep when port roles change? That is, if no USB cables are plugged in, we stay in sleep or deep sleep, and then wake up when the user plugs in a cable?
Our firmware engr seemed to think that we need to wake up periodically to check the ports. He did not think that plugging in a cable would generate an interrupt.
If the ports are fixed role, like source or sink, CCG4 will wake up on attach, by an interrupt from the CC termination logic.
If the ports are Dual Role, no cable plugged in, then CCG4 will need to periodically wake up from deep sleep in order to change the termination between Rp and Rd.
Rp - Rd toggle generally happens at 50 - 70 ms period. Once a cable is plugged in, the ports can settle into a definite role, which will allow the core to sleep (unless re-negotiation / fault events / HPI commands are in picture).