Hi
I'm experiencing some unexpected behavior while changing the CX3 MIPI interface configuration. I had a hard time finding the correct settings to finally receive data form my camera board. I'm using an FPGA that emulates a CMOS camera with MIPI CSI2 TX and following specs:
- CSI2 D-PHY v1.1
- D-Phy clock 202.5 MHz
- 2 data lanes
- non-continuous clock mode
- Byte clock 50.6250 MHz
- Pixel clock 81.0 MHz
- Video format: RAW10
- Word count: 2400
- Resolution: 1920x1080
- H-blanking: 220
- V-Blanking: 181.7
- FPS: 30
With the following parameters in the CX3 configuration tools I got it partially working:
By partially working I mean that I succesfully receive about 75% of the frames (and they are also correctly displayed). But I still get some MIPI control errors (incorrect line state sequence according to the API). The debug terminal outputs following info:
Prod = 112 Cons = 112 Prtl_Sz = 23808 Frm_Cnt = 3885 Frm_Sz = 4147200 B
0 0 0 0 0 0 0 0 0
Prod = 112 Cons = 112 Prtl_Sz = 23808 Frm_Cnt = 3886 Frm_Sz = 4147200 B
0 0 0 0 0 0 0 0 0
Prod = 112 Cons = 112 Prtl_Sz = 23808 Frm_Cnt = 3887 Frm_Sz = 4147200 B
0 0 0 0 0 0 0 0 0
Prod = 0 Cons = 0 Prtl_Sz = 3840 Frm_Cnt = 3889 Frm_Sz = 3840 B
0 0 0 65 0 0 0 0 0
Prod = 0 Cons = 0 Prtl_Sz = 3840 Frm_Cnt = 3899 Frm_Sz = 3840 B
TimeDiff = 0 ms FPS = -1
0 0 0 87 0 0 0 0 0
Prod = 0 Cons = 0 Prtl_Sz = 3840 Frm_Cnt = 3909 Frm_Sz = 3840 B
0 0 0 43 0 0 0 0 0
Prod = 0 Cons = 0 Prtl_Sz = 3840 Frm_Cnt = 3915 Frm_Sz = 3840 B
0 0 0 66 0 0 0 0 0
Prod = 0 Cons = 0 Prtl_Sz = 3840 Frm_Cnt = 3927 Frm_Sz = 3840 B
0 0 0 55 0 0 0 0 0
Prod = 0 Cons = 0 Prtl_Sz = 19200 Frm_Cnt = 3931 Frm_Sz = 19200 B
TimeDiff = -1 ms FPS = 0
0 0 0 92 0 0 0 0 0
Prod = 0 Cons = 0 Prtl_Sz = 3840 Frm_Cnt = 3942 Frm_Sz = 3840 B
0 0 0 24 0 0 0 0 0
Prod = 112 Cons = 112 Prtl_Sz = 23808 Frm_Cnt = 3943 Frm_Sz = 4147200 B
0 0 0 0 0 0 0 0 0
As can be seen, at first it receives three frames without error (full size: 1920*1080*2=4147200B). But then it only receives two lines (3840B) and throws some errors. This happens a couple of times and then it receives again a full frame at the end.
Now what is really strange is that the behavior is very sensitive to the configuration parameters. For example when I increase the output pixel clock frequency, I receive more transmission errors and sometimes it doesn't even work at all. How can slightly inreasing the output pixel clock frequency have an effect on that? As long as the FIFO delay is not too short or too long (it is well within the margins suggested by the tool) it shouldn't have any effect in my understanding.
What is even more confusing is that it also happened that I noticed malfunction when changing the params in a way that the output pixel clock frequency was unchanged. E.g. decrease the predivider value and multiplier of unit clock both by a factor of two. In my understanding this should by no means have any effect on the behavior.
