Need Verilog output from cyudb and cysch files

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jicac_264551
Level 2
Level 2

I found an autogenerated verilog file in "myproject.cydsn/codegentemp/myproject.v" that represents everything inTopDesign.csych and all the components within.

Under each "mycomponent.cyudb", there is an autogenerated  "verilog" tab that shows the verilog for just that component.  Is there a way I can get that code to show up as "myproject.cydsn/codegentemp/mycomponent.v" or something similar?

The reason I ask is that I'm using git as a version control.  I can't compare one commit of "mycomponent.cyudb" to another since they are binary files.  If I include the autogenerated verilog files in each commit, then I can easily look for diffs in plain text.

Thanks!

Jim

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Ekta_N
Moderator
Moderator
Moderator
750 replies posted First like given 250 solutions authored

Hello Jim,

The verilog code for the custom component created can be viewed from the verilog tab (mycomponent.v) for the custom component. No verilog file for the custom component created is present in codegentemp folder of the project.

However the .v file for the entire project (myproject) is present in the codegentemp folder for that project.

Best Regards

Ekta

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Ekta_N
Moderator
Moderator
Moderator
750 replies posted First like given 250 solutions authored

Hello Jim,

The verilog code for the custom component created can be viewed from the verilog tab (mycomponent.v) for the custom component. No verilog file for the custom component created is present in codegentemp folder of the project.

However the .v file for the entire project (myproject) is present in the codegentemp folder for that project.

Best Regards

Ekta

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Hi Ekta,

I did notice the myproject.v in the codegentemp folder.  I've been including just that one file in the codegentemp folder and doing diffs on that.  This has the advantage of catching the diffs for the entire design, but it is not quite as easy to identify the diffs for each component individually.

Thanks for your help!

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