2 Replies Latest reply on May 13, 2019 8:35 AM by jicac_264551

    Need Verilog output from cyudb and cysch files

    jicac_264551

      I found an autogenerated verilog file in "myproject.cydsn/codegentemp/myproject.v" that represents everything inTopDesign.csych and all the components within.

       

      Under each "mycomponent.cyudb", there is an autogenerated  "verilog" tab that shows the verilog for just that component.  Is there a way I can get that code to show up as "myproject.cydsn/codegentemp/mycomponent.v" or something similar?

       

      The reason I ask is that I'm using git as a version control.  I can't compare one commit of "mycomponent.cyudb" to another since they are binary files.  If I include the autogenerated verilog files in each commit, then I can easily look for diffs in plain text.

       

      Thanks!

      Jim

       

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