1 Reply Latest reply on Jun 10, 2019 2:34 AM by BragadeeshV_41

    PSoC63 SPI SCLKmode incorrect?




      I'm communicating with an SPI  device (PSoC 63 is MASTER) which expects CPOL=0 CPHA=1, however when I try set it like that in ModusToolbox I noticed the SCLK line is idle high not low. Code generated has CY_SCB_SPI_CPHA1_CPOL0 set for sclkMode in the _config .


      After tweaking with the settings I got it to work, but only when I use CPOL=1 CPHA=0 (CY_SCB_SPI_CPHA0_CPOL1 sclkMode). That way the clock line is idle low and active high as expected for CPOL=0 and the phase seems to actually match what I'd expect to be 1.


      Am I just very confused about how this is supposed to work or is there a real problem here?


      This is using ModusToolbox 1.1. Screenshot shows logic trace of the device working correctly on CY_SCB_SPI_CPHA0_CPOL1, but to me this isn't really CPOL1 at all.


      Screenshot 2019-04-30 at 08.02.14.png

        • 1. Re: PSoC63 SPI SCLKmode incorrect?

          Hi joma_1267006,


          We confirm this issue. The issue is with the SCB drivers. Instead of writing CPHA = 0 and CPOL = 1 in the SCB_SPI_CTRL register, CPHA = 1 and CPOL = 0 is being written in the registers. That is the reason for this behavior.


          Thank you for pointing it out. We will get this fixed.




          The fixed enum is:

          typedef enum

              CY_SCB_SPI_CPHA0_CPOL0 = 0U,   /**< Clock is active low, data is changed on first edge   */
              CY_SCB_SPI_CPHA1_CPOL0 = 1U,   /**< Clock is active low, data is changed on second edge  */   
              CY_SCB_SPI_CPHA0_CPOL1 = 2U,   /**< Clock is active high, data is changed on first edge  */
              CY_SCB_SPI_CPHA1_CPOL1 = 3U,   /**< Clock is active high, data is changed on second edge */
          } cy_en_scb_spi_sclk_mode_t;


          This will be fixed in the next PDL release. You can use this workaround for now.