Please provide a sample firmware that includes the above-said logic implemented.
I can test internally and let you know the observations/ modifications needed.
The thread title says that you are seeing speed change event with some motherboards. Please let us know what are those motherboards and what are the motherboards working fine.
>> To make this work we have implemented a simple logic where we will disable the USB PHY using CyU3PConnectState(CyFalse, CyFalse) and toggle the MUX GPIO again for every endpoint re-configuration process.
Can you please explain what is meant by "every endpoint re-configuration process."?
Can you please confirm whether there are NO resets when you connect the board in single orientation (in which it enumerate in USB 3.0)?
After the MUX logic added to the code and flipping connector, how many resets you have seen?
Reset over the USB 3.0 is common if the link couldn't come up in USB 3.0. It is supposed to establish after one or two resets.
Note that if the USB 3.0 link could not establish after three retries, the link will come up in USB 2.0 unless you specifically disable the USB 2.0 connection and enable only USB 3.0 connection using a loop in firmware(KBA - Enabling FX3 Only for USB 3.0 Applications – KBA219491 ).