3 Replies Latest reply on May 3, 2019 10:22 AM by LePo_1062026

    How to determine whether or not Watchdog has "bitten?"

    xahuc_3536641

      I have implemented a watchdog timer very simply as follows:

       

      uint16 Heartbeat_LED_counter = 0;
      void SysTickISRCallback(void)
      {
          counter++;
          Heartbeat_LED_counter++;
      }
      int main(void)
      {
          CyGlobalIntEnable; /* Enable global interrupts. */
         
          
          /***********************************************/
          /* Custom Code to enable timeout for I2C hang */
          CySysTickStart();
          
          for (uint8 i = 0u; i < CY_SYS_SYST_NUM_OF_CALLBACKS; ++i)
          {
              if (CySysTickGetCallback(i) == NULL)
              {
                  /* Set callback */
                  CySysTickSetCallback(i, SysTickISRCallback);
                  break;
              }
          }
          /***********************************************/
          
          /* Indicator LED ON During Setup */
          Indicator_LED_OUT_1_Write(0x01);
          
          /* Place your initialization/startup code here (e.g. MyInst_Start()) */
          Torch_Setup();
          CS_Setup();
          
          MODBUS_Start();
          I2C_Start();
          CS_Config();
          
          /* Flash Indicator LED OFF After Setup */
          Indicator_LED_OUT_1_Write(0x00);
          CyDelay(100);
          Indicator_LED_OUT_1_Write(0x01);
          CyDelay(100);
          Indicator_LED_OUT_1_Write(0x00);
          CyDelay(100);
          Indicator_LED_OUT_1_Write(0x01);
          CyDelay(100);
          Indicator_LED_OUT_1_Write(0x00);
          CyDelay(100);
          
      //    Torch_Set_Power(ON);
      //    
      //    CyDelay(50);
          
          CyWdtStart(CYWDT_1024_TICKS, CYWDT_LPMODE_NOCHANGE);
          
          for(;;)
          {    
              
              /* Place your application code here. */
              if(MODBUS_Get_Message_Available())
              {
                  MODBUS_Process_Msg();
              }
              
              /* Feed the WatchDog */
              CyWdtClear();
              
              /* Check Heartbeat LED */
              if(Heartbeat_LED_counter >= 1000)
              {
                  Heartbeat_LED_counter = 0;
                  Indicator_LED_OUT_2_Write(~Indicator_LED_OUT_2_Read());
              }
          }
      }
      

       

      Given a reset of the processor, I would like to be able to determine whether that reset was triggered due to the WDT timing out OR due a simple power-cycle. Is there anyway to do this?

       

      Ultimately I would like the master on our system (I am designing the slave) to be able to query whether or not the slave has reset due to watchdog bite at any point since it was first powered on.

        • 1. Re: How to determine whether or not Watchdog has "bitten?"
          AnkitaS_51

          Hi,

           

          This forum thread discusses the same query, please check it will be useful:

          Checking the source of reset in PSoC3/PSoC5

           

           

          PSoC3/PSoC5 device has  multiple sources which can reset the device.

            

               
          • WatchDog
          •    
          • Low Voltage Detect Analog, LVI-A
          •    
          • Low Voltage Detect Digital, LVI-D
          •    
          • Software Reset and so on
          •   

            

          Once the device is reset it is possible to identify the source of reset by reading the value of the register, RESET_SR0. However this register is read on clear. When the reset is triggered and the device boots, the device by default waits for bootloader and in the bootloader code this register is read and the status is cleared. However before reading this register the code preserves this register value as a variable, uint8 CyResetStatus.

          1 of 1 people found this helpful
          • 2. Re: How to determine whether or not Watchdog has "bitten?"
            xahuc_3536641

            Thank you, I searched and searched the forums for this answer and couldn't find it despite it being so straightforward.

            • 3. Re: How to determine whether or not Watchdog has "bitten?"
              LePo_1062026

              Xavier,

               

              I believe Ankita answered your question.  The RESET_SR0 register immediately after reset contains the reason for the reset with the exception of Power On Reset (POR).  This type of reset is inferred by the fact that no other type of reset was latched in this register.

               

              For the definition of the reset type flags consult "PSoC 5LP Registers TRM, Document No. 001-82120 Rev. *F"  Chapter 1.3.162 RESET_SR0

               

              As indicated, this register is normally read also immediately after reset by application initialization code.  In this case the register contents of RESET_SR0 is stored in SRAM variable called CyResetStatus (it has the same bit flag format as RESET_SR0).

               

              Len