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Problem has been solved by myself.
Attached is non-blocking emulated EEPROM example that is working fine on CY8CKIT-041-4000S kit, if someone need non-blocking write flash or emulate EEPROM, please refer.
Because the CPU cannot execute code from flash while doing an erase or program operation on the flash, the nonblocking system calls can only be called from a code executing out of SRAM. So the code you want to run while writing flash/eeprom has to be placed into SRAM.
The SPC ISR is needed for non-blocking write row and executed three times before the end of write operation.
Compared with PSoC4_EmEEPROM code example, I revised CyFlash.c and .LD file, and add SPC interrupt related code in main.c. In order to test the CPU is running code while writing eeprom, I add timer ISR placed into SRAM.
Other restrictions, IMO need set to 48Mhz and SPC interrupt must not be interrupted by other ISR with higher priority.