2 Replies Latest reply on Apr 26, 2019 1:37 AM by StevenZ_31

    Non-blocking emulated EEPROM

    StevenZ_31

      Hi,

       

      I am trying to perform a non-blocking emulated EEPROM using P4000S, because code example em_EEPROM is calling blocking write row, not non-blocking write row, this cause 20ms blocking delay, can’t handle 1ms timer interrupt for critical task.

       

      TRM did say that non-blocking system calls can be called from a code executing out of RAM, so I located timer interrupt and other functions into RAM, then call non-blocking write row instead of blocking write row in CyFlash.c, but still not working, CPU is not halted after calling non-blocking flash write row, 1ms timer interrupt is handled, but EEPROM data is not written correctly into flash.

       

      Could anyone tell me whether it is possible to implement a non-blocking emulated EEPROM and how to do.

      The SPC interrupt, how to use? 

      The code in TRM: 20.7 Non-Blocking System Call Pseudo Code, seems not right, SPC interrupt is not triggered after calling non-blocking write row, is there something wrong?

       

      CY_SECTION(".sramCode") __USED

      void SpcIntHandler(void)

      {

          //Write key1, key2 parameters to SRAM

          REG( 0x20000000 ) = 0x0000DCB6;

          //Write the address of key1 to the CPUSS_SYSARG reg 

          CPUSS_SYSARG_REG = 0x20000000;

          //Write the API opcode = 0x09 to the CPUSS_SYSREQ.COMMAND * register and assert the sysreq bit

          CPUSS_SYSREQ_REG = 0x80000009;

          // Number of times the ISR has triggered

          iStatusInt ++;

      }

       

      void SPC_SetVector(cyisraddress address)

      {

          CyRamVectors[CYINT_IRQ_BASE + 9] = address;

      }

       

      int main(void)

      {

          uint8 i;

         

          /* Enable global interrupts. */

          CyGlobalIntEnable;

         

              /* Set the ISR to point to the Interrupt. */

          SPC_SetVector(SpcIntHandler);

       

                  /*CM0 interrupt enable bit for spc interrupt enable */

              CM0_ISER_REG |= 0x00000040;

             

              /*Set CPUSS_CONFIG.VECS_IN_RAM because SPC ISR should be in SRAM */

             CPUSS_CONFIG_REG |= 0x00000001;

         

      ...................