(1) Set input pin DCC_unfiltered input to "Syncronized".
(2) Leave Sync in place of NOT, but use BUS_CLK clock (MASTER_CLK on PSoc4?)
Using a SYNC component instead of NOT should work fine.
You can refer to the document 'Digital Design Best Practices' , page 24: https://www.cypress.com/file/179061/download .
In figure 34, the input to the sync component is 'tc' which is also high for one clock cycle.