6 Replies Latest reply on May 6, 2019 4:44 AM by DheerajK_81

    JTAG BUFFER

    NiNa_4043086

      Hi,

      I am planing a board with PSOC5LP and I would like to use JTAG configuration to program the PSOC.

      Unfortunately, the connection to the programmer (MINI prog3) goes through several cables (and connectors) and the overall length will be long.

      I think to use buffer to strengthen the signals but I see that there is no need in pull up/down so I do not know which initial state to set for each signal in the buffer input.

      How should I connect the buffer? Which kind of buffers do you recommend?

       

      Many thanks!

        • 1. Re: JTAG BUFFER
          DheerajK_81

          There are no general guidelines for adding buffers because it is dependent on the board design, loads, switches etc. But based on the number of devices in the chain, you can add the buffers in a tree fashion and drive the signals TMS, TCK to meet the JTAG timing requirements. You can add buffer optionally to TDI and TDO based on your design if they drive many loads.

           

          Any non-inverting gate with proper voltage range should do. There are many dual buffer chips which you could use.

           

          Regards,
          Dheeraj

          • 2. Re: JTAG BUFFER
            NiNa_4043086

            I would like to add Buffer to each of the 4 signals but the buffer interface will not be floating.

            As I understand, this connection needs to be complied with the programmer (MINI prog3) requirements which will now "see" the pull-up/down on the JTAG lines instead of direct connection to PSOC.

            And in addition, the PSOC should handle that the JTAG lines now have default logic state set by the pulled-up/down.

            After mentioning this, Is it OK that on the connector side TDI, TDO, TMS will be pulled to 3.3V through 1KOhm resistor and TCK will be pulled to GND through 1KOhm? See below.

             

            • 3. Re: JTAG BUFFER
              DheerajK_81

              Please follow the requirements as specified in the table:

              jtag.PNG

               

              For more information refer Section 1.2.2 JTAG Interface in this document: https://www.cypress.com/file/119651/download

               

              Regards,

              Dheeraj

              • 4. Re: JTAG BUFFER
                NiNa_4043086

                Thanks,

                So it looks like for the PSOC side this configuration of pull-up/down resistors are OK but I am still not sure about the MINI PROG3 side. I could not find if it is OK that the MINI PROG3 will "see" 1KOhm pull-up/down resistors instead of the internal 5.6KOhm resistance of the PSOC.

                • 5. Re: JTAG BUFFER
                  NiNa_4043086

                  Hi,

                  Any news? Do you have an answer?

                  • 6. Re: JTAG BUFFER
                    DheerajK_81

                    I cannot guarantee because since we are dealing with timing requirements, the length of the wires, frequency at which JTAG is being operated, everything has an effect. You can start with this setup and check for its working by adjusting the clock speed. Please test it on a prototype before going into production as this isn't something we test and we cannot guarantee its working due to reasons (board design, loads, switches etc.) which I had already mentioned.

                     

                    Regards,

                    Dheeraj