2 Replies Latest reply on Jul 8, 2019 11:12 PM by DheerajK_81

    Debug HardFault on M0+




      I am working on CY8CKIT-062-WIFI-BT Development board.I have ported FreeRTOS + LWIP + MbedTLS + Azure IOT C SDK on M0+ core of pSoC 6.

      The whole code is working, but sometimes I am seeing the processor lockup. By attaching debugger lockup shows to be in function Cy_SysLib_ProcessingFault() .


      I am trying to debug the fault as per the parameters saved by Cy_SysLib_FaultHandler() function.

      the parameters of the fault are saved in variable cy_faultFrame.


      following is one such instance :-

      cy_faultFrame {...} 0x08000854 (All) struct { uint32_t r0; uint32_t r1; uint32_t r2; uint32_t r3; uint32_t r12; uint32_t lr; uint32_t pc; uint32_t psr; }

      Name      -      Value      -      Address      -      Type

      r0            0x1005E768      0x08000854      (All) unsigned long

      r1            0x000000B0      0x08000858      (All) unsigned long

      r2            0x00000043      0x0800085C      (All) unsigned long

      r3            0x08036E70      0x08000860      (All) unsigned long

      r12          0x10023E7F      0x08000864      (All) unsigned long

      lr             0x1005859A       0x08000868      (All) unsigned long

      pc           0x01000200       0x0800086C      (All) unsigned long

      psr          0x1005E75C      0x08000870      (All) unsigned long


      I want to know:-

      1. what does R12 contains ?

      2. why is PSR value looks like an address ( it should contains fault / proper functioning)? current xPSR value (on attaching debugger) is 0x01000003 which is expected.

      3. The fault is in which instruction, address pointed by (LR) or (LR - 2)? The core is running in Thumb mode and as per ARM M0p is having 2 stage pipeline.

      4. Is there a possibility that the cy_faultFrame variable was wrongly populated (PSR and PC did not seems correct). May be because Fault_Handler code in startup_psoc62_cm0plus.s file is not properly implemented and missed some value hence shifting whole stack.




        • 1. Re: Debug HardFault on M0+



          The HardFault debug function “Cy_SysLib_FaultHandler” in file “PROJECT\Generated_Source\PSoC6\pdl\drivers\peripheral\syslib\cy_syslib.ccy_syslib.c” is populating the structure incorrectly.




          All the values in variable cy_faultFrame are shifted by one register.

          to correct this I have commented adds r0, r0, #4 at line 358 in file startup_psoc62_cm0plus.S.


          After this the cy_faultFrame is populating correctly.




          I am requesting Cypress people to please correct this problem in their next release.



          Saurabh Solanki



          • 2. Re: Debug HardFault on M0+

            The issue occurs due to unaligned addresses. Switching over to PDL 3.1.0 resolves the problem.