10 Replies Latest reply on Apr 23, 2019 6:57 PM by AlbertB_56

    S25FL erase stops working after QUAD bit set

    dgoldman98_4177366

      Using chip S25FL256SAGMFI003.  Works great from factory.  I can erase sectors (0xDC), program (0x12), read (0x13), etc.  As soon as I use WRR to set QUAD bit to 1 in configuration register (setting/leaving everything else at 0), sector or bulk erase commands fail to set memory to all 1's (memory content remains unchanged).  I can still use program array commands (0x12) to effectively flip bits from 1 to 0, but cannot get erase (including bulk erase) to have any effect even though they worked fine before QUAD bit was set.  I read status and config registers, which return 0x02 and 0x02 respectively (which I think is correct).  I also tried adding software reset command before trying to erase sectors, etc.  I'm out of ideas.  Anyone have any suggestions?

       

      Best regards,

      David

        • 1. Re: S25FL erase stops working after QUAD bit set
          AlbertB_56

          Hello David,

           

          Thank you for contacting Cypress Semiconductor

           

          Given CR1[1] = 1 (Quad), what is/are the effect(s) on the S25FL256S when using the following (alternate)

          Sector Erase (SE), Bulk Erase (BE), Quad Page Program, Quad I/O READ  commands :

            - BE Bulk Erase (alternate command) =  Cmd : C7h   /  Freq. : 133MHz

            - SE Erase 64 KB or 256 KB (3- or 4-byte address) =  Cmd : D8h  /  Freq. : 133MHz

            - QPP Quad Page Program (3- or 4-byte address) =  Cmd : 32h  /  Freq.  80MHz

            - QPP Quad Page Program - Alternate instruction (3- or 4-byte address) =  Cmd : 38h  /  Freq. 80Mhz

            - QIOR Quad I/O Read (3- or 4-byte address) =  Cmd : EBh  /  Freq.  104MHz

            - 4QIOR Quad I/O Read (4-byte address) =  Cmd : ECh  /  Freq. 104MHz

           

          Thank you in advance...

           

           

          Best regards,
          Albert

          • 2. Re: S25FL erase stops working after QUAD bit set
            dgoldman98_4177366

            Hi Albert,

             

            Below is logic analyzer output for bulk erase as well as C-code excerpt that implements.  BulkErase.png

            CODE EXCERPT:

                SPI_Flash_Cmd(phspi,0x30,0x00000000,1,0);   //CLSR 30h - Clear Status Register

                SPI_Flash_Cmd(phspi,0x06,0x00000000,1,0);   //WREN 06h - Write Enable

                SPI_Flash_Cmd(phspi,0xC7,0,1,0);   //Bulk erase C7h

                do {

                    SPI_Flash_Cmd(phspi,0x05,0x00000000,2,0);   //RDSR1 05h - Read Status Register 1

                } while (pRxData[1]&0x01); //while WIP is true (write in progress)

             

            At the end of this sequence, I issue a 4READ (13h) command that shows memory contents unchanged.

             

            Similar result occurs when doing sector erase (e.g. code below):

                SPI_Flash_Cmd(phspi,0xDC,nSector,5,0);   //4SE DCh - 64Kb sector erase

             

            Hardware configuration does not allow me to do Quad page program commands. However, regular page program 4PP (12h) works correctly in that I can program pages (and bits in flash array effectively flip from 1's to 0's as expected).  I just can never flip them back to 1's using erase commands.

             

            4QOR (6Ch) commands also work properly, reading the current contents of the flash array 4 bits at a time out of the 4 lines of the chip.  Hardware motherboard makes it difficult to execute other commands (4QIOR, etc.).

             

            I'm running this chip at speeds of 25MHz or less.

             

            Let me know what you think.

             

            Best regards,

            David

            • 3. Re: S25FL erase stops working after QUAD bit set
              AlbertB_56

              Hello David,

               

              Running the S25FL256S at 25MHz is no problem at all, as the Quad I/O READ max frequency is 104MHz,

              and Quad Page Program max frequency is 80MHz.

               

              Just for my understanding, the FLASH is configured in QUAD mode, via CR1[1] = 1.  However the PCB/Hardware

              does not allow you to initiate a Quad Page Program and Quad I/O READ.  Therefore, what is the effect of the Bulk

              Erase (Cmd : 60h  or  C7h) and Sector Erase (Cmd : D8h  or  DCh) on the S25FL256S when CR1[1] = 0?

              Do the Bulk Erase and Sector Erase commands work?

               

              In the last waveform screen capture, I see RDSR1 (Cmd : 05h), but I do not see 4READ (Cmd : 13h) 

               

               

               

              Best regards,

              Albert

              Cypress Semiconductor

              • 4. Re: S25FL erase stops working after QUAD bit set
                dgoldman98_4177366

                Hi Albert,

                 

                Below is excerpt from 4READ (13h)... I left it out originally, since I thought there was nothing interesting there.

                 

                4READ_13h.png

                The PCB hardware has 2 modes, one that allows SDR 1-bit operations with flash via STM32 microcontroller (for programming, accessing registers, etc.)  The other mode, connects the flash chip to a Lattice CPLD that only issues 4QOR (6Ch) commands to read the array 4 bits at a time (while keeping the STM32 disconnected).    The CPLD works perfectly, as I have observed the waveforms, pulling data from the flash array by issuing 4QOR commands and getting the data in 4 bit chunks.  I can also exit this mode (which connects the STM32 back to the flash) to do other operations like reprogram pages in the flash array using 1-bit operations.  My main issue is that I cannot ever erase the array when in QUAD mode.  Before I put the flash in QUAD mode, everything works perfecting (erasing sectors, etc.), but after QUAD=1 erase does not work.  Again, before chip is in QUAD mode (CR1[1]=0), bulk erase and sector erase commands work as expected. 

                 

                Another issue, that I am not sure if it is expected behavior... once I put the flash in QUAD mode, I can never take it out of QUAD mode (i.e. set CR1[1] = 0).  I've tried using WRR command, but it seems to only work when setting bit, not clearing it.  Below is a waveform capture of how I try to set CR1[1]=0, using WREN and WRR commands, followed by RDCR (35h) showing read from CR1 (i.e. still CR1[1]=1). 

                 

                WRR_01h_to_clear_QUAD.png

                Let me know if this helps or any further clarification is useful.

                 

                Best,

                David

                • 5. Re: S25FL erase stops working after QUAD bit set
                  dgoldman98_4177366

                  I continue to experiment here, but still no luck.  Please let me know if you have any other ideas.  Best, David

                  • 6. Re: S25FL erase stops working after QUAD bit set
                    AlbertB_56

                    Hello David,

                     

                    Please provide the complete Ordering Part Number (OPN) of the STM32 microcontroller you are currently using, as we are researching

                    the possibility that not all Cypress SPI FLASH memory products are fully supported by the the STM32 micrcontroller family series.  The STM32F43x  fully supports memory densities up to the S25FL256SDS;  and the STM32H7xx only supports the S25FL512SAGMFI011.

                    Other STM32xx microcontrollers support memory densities up to 128Mb and below.

                     

                    Although the S25FL256S may be working in SDR mode, there may also be the possibility that QUAD I/O may not be supported by

                    a specific STM32xx microcontroller, as with most Chipset partners, the qualification configuration of a FLASH memory device may

                    involve SDR mode only, and not QUAD I/O mode.   As well, please contact ST Micro in regards as to whether or not the STM32xxx

                    Series (OPN specific to  your use) is qualified for use with Cypress FLASH memory products in "Passive-Serial" Configuration with

                    the Lattice CPLD.

                     

                    Please communicate your findings at your earliest convenience.

                     

                     

                    Best regards,

                    Albert

                    Cypress Semiconductor

                     

                     

                     

                    • 7. Re: S25FL erase stops working after QUAD bit set
                      dgoldman98_4177366

                      Hi Albert,

                       

                      I am using STM32F410RBT6.

                       

                      Please share more detail since this seems extremely odd to me.  I was under the impression that if the waveforms measured at the flash chips inputs match the specifications within the Cypress data sheet, that this was the overarching requirement to use the flash chip..

                       

                      The other thing that does not make sense to me is that everything I can possibly imagine testing with the chip in SDR/single bit works perfectly.  However, when QUAD bit is set, SDR erase commands stop working (literally everything else needed on the flash chip continues to work perfectly).  I have already confirmed that QUAD reads also work perfectly when connected to the lattice chip (the only quad function that I require in my application). 

                       

                      Best,

                      David

                      • 8. Re: S25FL erase stops working after QUAD bit set
                        AlbertB_56

                        Hello David,

                         

                        Thank you for confirming the FPGA OPN.

                         

                        Of your lot of S25FL256SAGxx, how many devices exhibit this behavior, when the QUAD bit CR1[1] = 1?

                        It appears the S25FL512SAG may be recognizing only some QUAD mode commands.

                         

                        Currently, your prototype is using a Lattice CPLD, which is the "Passive-Serial" configuration.

                        What is the result when the Lattice CPLD is removed, which is the "Active-Serial" configuration?

                        (Do Bulk Erase and Sector Erase operations now work when CR1[1] =  1 (in QUAD mode)?

                         

                         

                         

                        Best regards,

                        Albert

                        Cypress Semiconductor

                        • 9. Re: S25FL erase stops working after QUAD bit set
                          dgoldman98_4177366

                          Hi Albert,

                           

                          So I started from scratch using a basic Nucleo-F410RB development board from STM connected directly to a single flash chip. Everything works (the flash erases properly, even after the QUAD bit is set).  I need a few days to see what the difference is (since the lattice chip is kept behind TI buffers (that are set to Hi-Z/disabled) so in theory, flash chip should never be effected by lattice when being commanded by STM.  Can you keep this thread open through the weekend, since I may post an additional question (or the resolution if I figure out what the issue is)?

                           

                          Best,

                          David

                          • 10. Re: S25FL erase stops working after QUAD bit set
                            AlbertB_56

                            Hello David,

                             

                            Thank you for  your response...

                             

                            Yes, most certainly!  I will set this thread to "waiting on customer", and it will remain 'open' for the most part.

                             

                             

                             

                            Best regards,
                            Albert

                            Cypress Applications Support