3 Replies Latest reply on Apr 15, 2019 11:24 AM by user_246598725

    Verilog: initialize register value?

    user_246598725

      Hi,

       

      is it possible to initialize a register value in PSoC verilog implementation? I tried "reg A = 1'b1;" on register definition, but it isn't accepted. I didn't find anything in the documentation.

       

      Regards