- Please let us know if you are using the FPGA code that is present with the application note.
- Have you made any modifications to the FPGA/FX3 code?
- What is the data that is being received on the FPGA? Please share captures on the FX3 GPIF II data lines.
The reason why the data received by the FPGA is always 0 is that the FPGA development board (KC705) does not match the voltage of the USB development board (CYUSB3KIT-003).I used the oscilloscope to grab the signal and found that the maximum voltage of fdata is 1V when USB sends data to the FPGA(Channel 1). The maximum voltage of fdata when the FPGA sends data to USB is 2V. 1V is less than the VIHmin(1.7V) of KC705, so KC705 believes that the received data is always 0.The solution is to use the interface(gpio_rtl) provided by xilinx to define the fdata pin.