2 Replies Latest reply on Apr 18, 2019 7:10 PM by XiXI_4139851

    FX3 Slave FIFO loop_back example

    XiXI_4139851

      HI

       

      I'm working with the FX3 SuperSpeed Explorer Kit to try and send data to (and receive data from)  FPGA. I download code example from:AN65974 - Designing with the EZ-USB® FX3™ Slave FIFO Interface.

      In the Loop_back case,the FPGA does not correctly receive the data sent by the Control Center, but Control Center can correctly receive the data of the FPGA. The data from Control Center is always 0.

      What cause problems with transfer accuracy?

      图片1.png

       

        • 1. Re: FX3 Slave FIFO loop_back example
          SrinathS_16

          Hello,

           

          - Please let us know if you are using the FPGA code that is present with the application note.

          - Have you made any modifications to the FPGA/FX3 code?

          - What is the data that is being received on the FPGA? Please share captures on the FX3 GPIF II data lines.

           

          Best regards,

          Srinath S

          • 2. Re: FX3 Slave FIFO loop_back example
            XiXI_4139851

            The reason why the data received by the FPGA is always 0 is that the FPGA development board (KC705) does not match the voltage of the USB development board (CYUSB3KIT-003).I used the oscilloscope to grab the signal and found that the maximum voltage of fdata is 1V when USB sends data to the FPGA(Channel 1). The maximum voltage of fdata when the FPGA sends data to USB is 2V. 1V is less than the VIHmin(1.7V) of KC705, so KC705 believes that the received data is always 0.The solution is to use the interface(gpio_rtl) provided by xilinx to define the fdata pin.