3 Replies Latest reply on Apr 9, 2019 10:51 AM by RaAl_264636

    Best way to test Verilog and/or UDB component?




      I wonder if there's a "best practice" to test self-made components. Of course, if a component works as intended for the project it's made for, this is a good result. But in my opinion this is not enough, because in the next project where the component is used there might be other circumstances. So, how do you test your components?


      For example, for input signals (either hardware or API controlled), I set the input signals (in case of hardware by control register), and the component clock is controlled also by a control register, not bus clock or similar (if there are input strobes, the clock is not generated synchronously to them, but after settings them). For output signals, if there's a strobe or ready output, I use sticky status registers with the strobe/ready signal as clock.

      The corresponding test firmware stimulates all "useful" (not neccessarily possible) input combinations, verifies the outputs against the expected results and outputs errors on UART. But I don't know if this is testing enough. And I've to admit that each test firmware tries to use the same approach, but I always end up with "special" code for a given component - I always feel that my test approach is not abstracted enough.


      Currently, I don't use external instruments like logic analyzer or pattern generator to verify the behaviour of a component. I know there's an chapter in the component author guide about simulating components, but this is totally outside of my knowledge. So, are you testing components with external instruments or simulation?