I think the official UDB based components provided in Creator IDE are tested use third-party simulation tools.
To myself, i usually make some special timing modules use verilog, the logic is simple, so i choose to use external instruments for module logic testing.
I too do not have a pattern generator. I commonly use another PSoC to generate the input signal if possible.
For example, for a project that involved creating a Manchester signal DECODER, I created a Manchester signal ENCODER with a PSoC and fed that signal into the DECODER. If you have the resources available on the PSoC you're coding for, you can stick the input generator on the same PSoC.
Hope this helps.
Hello Len & VisonZ_71,
thank you for your answers. So, it seems that my approach is not far away from yours.