Hi Massimo Milanesi,
Could you please share the firmware HEX file you were testing and VIF of your project in this threads?
Could you please confirm which firmware version you are using?
in attach you can find HEX and VIF file (for both ports).
I confirm we are using FW SDK 188.8.131.521.
As per the test report and firmware you attached, below is the comments for your reference.
PD 2.0 5A Active Cable -> For a PUT_R, the PUT must provide Rp on both CCS:
CCGx firmware always applied Rp on both CC lines. If this is failing, I would like to recommend you check whether the hardware is wrong (not connecting one of the CC lines). It seems there is only one CC connection on CCG5.
PD 3.0 5A Active Cable -> The PUT connects the SS pairs after 80 ms:
CCGx firmware have a compile time configuration called MUX_INIT_DELAY_MS which can be set in the project to define the time required for SS MUX to be enabled before VBus turns on. This should be set to an appropriate value based on your hardware to pass the test.