Is it possible for you to share schematic diagram of your application with us?
Are the output lines of HyperRAM connected to more than 1 devices?
Thank and Regards,
Did you configure output drive strength of HyperRAM according to your PCB? Output drive strength of HyperRAM can be adjusted by changing the bits 12, 13 and 14 of configuration register 0 (CR0[14:12]). Please refer below sections in datasheet for more information.
- 5.2.1 Configuration Register 0 (page 21)
- 18.104.22.168 Drive Strength (page 24)
Thanks and Regards,
I would like to revisit this topic. I changed the driver circuit in our design and I am still unable to get the HyperRam to respond to read or write transfer requests.
Please use the attached scope waveform as reference. The first shows a memory read access window whilst the second shows a write access transaction. In both cases the HyperRam RWDS pin does not provide a strobe pulses after the designated latency period. The programmed delay is set to 3 cycles.
Can you provide some insight as to what might be wrong.
Thanks and best regards,