1 2 Previous Next 17 Replies Latest reply on Apr 16, 2019 3:57 AM by user_119654

    PSOC 5LP as power discharge controller

    ninatan_4043086

      Hello,

      I am designing a board with PSOC5LP CY8C5868AXI-LP035.

      I would like to implement a power discharge controller using the PSOC.

      Once the main power to the board goes bellow certain point the PCOC will start internal power discharge sequence.

      I plan that at each discharge phase the PSOC will measure the discharged voltages and once they reach 10% of nominal it will start the next power discharge phase until all internal power are discharged.

      Because this process is limited by time (few mili seconds to discharge all internal powers) I need the PSOC to react as fast as possible.

       

      The PSOC will receive an input indication to start the process (main input power indicator) and should output the controls to the discharge circuits.

       

      Do you think the PSOC is suitable for this?

       

      What is the response time which take to PSOC to start the process?

        • 1. Re: PSOC 5LP as power discharge controller
          VasanthR_91

          Hi,

           

          PSoC 5LP has a comparator which can with a minimum response time of 110ns which can initiate your discharge sequence fast enough. If you want an ADC to scan, SAR ADC scan at a rate of 1Msps. What are the other concerns you have with respect to PSoC ?

           

          Best Regards,
          Vasanth

          • 2. Re: PSOC 5LP as power discharge controller
            ninatan_4043086

            Hi,

            Thanks.

            I am concerned about the time from event detection to execution. For example, What is the delay time from detecting certain voltage going below 10% till executing next voltage discharge. Is it all hardware or also software involved? 

            • 3. Re: PSOC 5LP as power discharge controller
              VasanthR_91

              Hi,

               

              It will depend on your discharge mechanism implementation too I guess. The comparator will be able to generate a logic high to start your discharge mechanism. Or it can trigger an ISR which will initiate all the necessary steps for your discharge process.  This will include software delay. If you want to check the voltage level and multiple points, you may make use an amux. This appnote will be helpful. A similar configuration can be used to remove the need for CPU, by switching channels only on the base of comparator results. If ADC is also used, it also requires additional software overhead of reading the result value and making the decision of initiating discharge.

               

              Best Regards,
              Vasanth

              • 4. Re: PSOC 5LP as power discharge controller
                ninatan_4043086

                Can you estimate the software delay for reading the ADC result value and making the decision of initiating discharge?

                • 5. Re: PSOC 5LP as power discharge controller
                  VasanthR_91

                  Hi Nimrod,

                   

                  That depends on your implementation . In PSoC 5LP, even if the SAR ADC is in free running mode, additional cycles will be required to read the result value, compare it with your threshold and initiate the discharging sequence according to your implementation. In PSoC 4 SAR ADC there is an option to trigger an interrupt when values go off limit. So in the ISR you can trigger your discharge sequence(if it is small enough). This might be suitable for the response time you are expecting.

                   

                  Best Regards,
                  Vasanth

                  • 6. Re: PSOC 5LP as power discharge controller
                    user_119654

                    Ninatan,

                     

                    How many power rails do you need to discharge?

                     

                    As Vasanth indicated, you can use a comparator but there are only 4 on the 5LP.

                     

                    For example to can set the nominal*10% for each rail using a VDAC as the '+' input to each comparator.  You can set the output of the comparator to a PSoC pin to drive the discharge load.

                     

                    With the suggestion above, the only SW you need is the initial setup.  The tripping of each power rail below 10% of nominal can happen entirely in HW without SW intervention.  A little bonus is that you can read back the PSoC pins you use to control the discharge load to see if the Discharge was at least started.  You would need to perform a ADC read to see if the power rail is ~ 0V.

                     

                    Len

                    • 7. Re: PSOC 5LP as power discharge controller
                      ninatan_4043086

                      Thanks Len.

                      I need to discharge 14 rails in 3 phases.

                       

                       

                      2 rails of 3.3V and 1.8V on first phase.

                      4 rails of 1.8V x 4 on second phase.

                      8 rails of 1.03V x 4, 0.95V x 4 on last phase.

                       

                      Maximum 8 at a time but the last 8 doesn't need to be measured for nominal*10%.

                      • 8. Re: PSOC 5LP as power discharge controller
                        user_119654

                        Ninatan,

                         

                        Must all the rails in each phase have reached the nom*10% level before starting the next phase?  Note: There is no good guarantee the rate of discharge, therefore one of the rails might be significantly below the nom*10% level before the last one in the phase gets to nom*10%.

                         

                        Len

                        • 9. Re: PSOC 5LP as power discharge controller
                          user_119654

                          Ninatan,

                           

                          I have a concept project I coded for you.  I compiles but since I don't have your actual HW, I have no good way to make sure I made no mistakes in the coding.  At least it should give you some ideas of how to achieve a low-latency discharge strategy.

                           

                          Len

                          • 10. Re: PSOC 5LP as power discharge controller
                            ninatan_4043086

                            Yes, on each phase all the rails must reach nom*10%. From calculations and analysis there is a significant variance between time discharge of the rails so a fall back solution maybe focusing on each phase only on the rail with the slowest discharge time.

                            • 11. Re: PSOC 5LP as power discharge controller
                              ninatan_4043086

                              Thanks a lot! I am not yet familiar with programing the PSOC so it will take me a while to check it.

                              • 12. Re: PSOC 5LP as power discharge controller
                                ninatan_4043086

                                Hi,

                                I have managed to do some tests on other board with PSOC. I have tried to see the response of the PSOC when using internal Power Monitor.

                                I measured a 3.3V input to the PSOC which should trigger a PGOOD high signal when reaching 3.3V*90% (3V).

                                 

                                The result was very bad - The PGOOD went high only 10ms from 3.3V input reaching 90%!

                                 

                                Can you help me understand why I got these results? I though the delay should not be more than 10us.

                                 

                                I have attached the test setup, the results, and power monitor settings.

                                The power monitor is working with a 1MHz clock and the monitoring is done on 4 voltage rails (one of them is the 3.3V).

                                 

                                PowerMonitor Test.jpg

                                 

                                PowerMonitor Setting.jpg

                                • 13. Re: PSOC 5LP as power discharge controller
                                  user_119654

                                  Ninatan,

                                   

                                  I'll take a look at it.  I should inform you that I've never worked with the Cypress PowerMonitor component.

                                  While I look at the component, maybe someone who has direct experience with in can help as well.

                                   

                                  Len

                                  • 14. Re: PSOC 5LP as power discharge controller
                                    user_119654

                                    Ninatan,

                                     

                                    Here's my "first-kick-at-the-can":

                                    The datasheet for the PowerMonitor component indicates the time for one measurement at maximum clock frequency @ 150us typ.

                                    The maximum clock frequency allowed is 66 MHz.  Your input clock is 1 MHz. You're 66 x slower.  This makes the measurement time at least 150*66us = 9900us = 9.9ms.   I believe this is why the PGOOD response takes 10ms.

                                     

                                    Even when the input clock is 66MHz, it looks like the best response time is about 150us not the 10us you were hoping for.

                                     

                                    More cautions:  Most implementations of using a ADC is to mux the inputs (See datasheet section "ADC Sequential Scanning").  This means that if you are measuring two inputs, each channel enabled for measurement may take 'x'-times longer before rescanning ('x' = number of channels enabled).

                                    from datasheet:

                                     

                                    "ADC Sequential Scanning

                                     

                                     

                                    The ADC will sequence through all power converters and auxiliary inputs, if enabled, in a round-robin fashion, taking voltage measurements and load current measurements. This component will measure the voltages of all the power converters in the system, but can be configured to measure currents from a subset of the power converters – including no current measurements at all. Doing so will minimize the number of IOs required and will minimize the overall ADC scan time. "

                                     

                                     

                                    If you use averaging, as it appears you are (Average 16), the PGOOD decision is made on the averaged value of ALL the 'N' readings.  This may prevent early detection of PGOOD until 'N' reading average reaches your target value.

                                    from datasheet:

                                     

                                    "Functional Description

                                     

                                     

                                    ...

                                     

                                    For both voltage and current measurements, averaging of the measurements is supported. The average value is calculated as a running average, which produces a new average with each scan that is the average of the previous N scans. When averaging is enabled, the average value is used in all cases where the value of the measurement is needed (faults, warning, power good and the reading of the measurement with APIs). "

                                     

                                     

                                    Len

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