Have you been able to understand the reason for frequent reset ? Also let me know what are you trying to achieve with the interrupt mechanism?
Psoc has different reset sources, power source monitoring is one of them. Power source monitoring - The analog and digital power voltages, VDDA, VDDD, VCCA, and VCCD are monitored in several different modes during power up, active mode, and sleep mode (buzzing). If any of the voltages goes outside predetermined ranges then a reset is generated. The monitors are programmable to generate an interrupt to the processor under certain conditions before reaching the reset thresholds. So please confirm power supply is fine.
You can always refer our hardware design guidelines while making your design. https://www.cypress.com/documentation/application-notes/an61290-psoc-3-and-psoc-5lp-hardware-design-considerations