You can check for the following possibilities:
Check if the ground of voltage divider same as the ground of PSoC
Check if you are reading the correct pin of the PSoC.
Yes! I have checked all that you have mentioned.
My observations are :
1. When I give vcc to one of the pins and read , it reads LOGIC HIGH
2.When I connect vcc to pin through a resistance or from a voltage divider, the pin doesn't read it as logic HIGH though the voltage in the pin reads more than the threshold corresponding to CMOS/TTL.
3.Does the resistor in the the buffer cause this? Because in design modus, I have selected 'strong input drive ,buffer on'.
If any changes are to be made in Design Modus, please tell!
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High Impedance (Hi-Z) state is recommended for analog and digital inputs inputs. For digital input the input buffer is enabled while for analog input buffer is disabled to reduce the crowbar currents.
Please refer to page 168 of PSoC 6 TRM:
THANKS A LOT!! This circuit was a part of a bigger circuit.It helped!!