3 Replies Latest reply on Mar 22, 2019 4:36 AM by ShanmathiN_06

    PILO Trim

    GrahamS_21

      Do we have any guidance on how often the PILO should be trimmed against a high accuracy clock source to maintain a 250ppm accuracy?

      This would be for the PSoC 6 module, with the AltHF BLE ECO of 32MHz as the high accuracy clock source.

       

      Do we have any example code to do this as well?

      Thanks

      Graham

        • 1. Re: PILO Trim
          ShanmathiN_06

          Hi Graham,

           

          We do not have any code example as such.

          But you could refer to the PDL documentation: System CLock-> Clock Trim (ILO, PILO)-> Functions. The function usage under Cy_SysClk_PiloTrim() trims the PILO with ECO.

           

          You could change the ECO to AltHF clock for your application. You need to change CY_SYSCLK_MEAS_CLK_ECO to CY_SYSCLK_MEAS_CLK_ALTLF in the Cy_SysClk_StartClkMeasurementCounters() API.

          You can also click on the API and refer to enum cy_en_meas_clks_t to know all the possible clock sources.

           

          I hope this helps.

          Thanks,
          Shanmathi

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          • 2. Re: PILO Trim
            GrahamS_21

            Do we have any guidance on how frequently we should be calling these functions to maintain the accuracy?

            thanks

            graham

            • 3. Re: PILO Trim
              ShanmathiN_06

              Hi Graham,

               

              It is generally recommended to calibrate every 0.1 to 1 second to maintain the accuracy.

               

              Thanks,
              Shanmathi