6 Replies Latest reply on Mar 25, 2019 5:01 PM by BushraH_91

    Pin swapping in parallel-interface memory types

    iltac_3027871

      Dear All,

       

      In our new design we are using external SDRAM, SRAM and NOR Flash on the EMIF.

      During layout phase we noticed the address, data and control pins are spread over BGA very untidy and we would like to swap address and data pins inside each own groups.

       

      Could it be possible? If yes is there anything to pay special attention?

       

      Thanks in advance.

      Regards

        • 1. Re: Pin swapping in parallel-interface memory types
          BushraH_91

          Hello,

          Thank you for contacting Cypress Community Forum. Currently we are reviewing the issue and will get back to you as soon as we find the resolution.

           

          Regards,

          Bushra

          • 2. Re: Pin swapping in parallel-interface memory types
            BushraH_91

            Hello,

            What is the device OPN  you are asking about? Can you please provide more detail of the address & data pins swap you are considering?

             

            In general, all the pins/signals need to satisfy the electrical specifications stated in the product datasheet.

             

            An application note of PNOR PCB layout guide is attached.

            • 3. Re: Pin swapping in parallel-interface memory types
              iltac_3027871

              Dear Bushra;

               

              the part number is S29GL128S. I wanna swap bits in the address and data group. Lets say for example instead of connecting CPU A1 to Mem A1, i would like to connect CPU A1 to Mem A9 and/or instead of connecting CPU D5 to Mem D5, i would like to connect CPU D5 to Mem D9 etc.

               

              By the way there is no attachment, i think you forgot  

               

              Regards

              • 4. Re: Pin swapping in parallel-interface memory types
                BushraH_91

                Hello,

                From signal integrity point of view, it sounds ok, since still address connects to address, data connects to data. However, we  don’t quite understand how you can guarantee the flash gets the correct address & data? Are you going to have a swap mapping mechanism handled in flash driver? I am resending the application note.

                 

                Thank you

                Regards,

                Bushra

                • 5. Re: Pin swapping in parallel-interface memory types
                  iltac_3027871

                  Dear Bushra;

                   

                  As it is already known in DDR3 data bits can be swapped in HARDWARE within data lane but since address and bank address signals are used to convey opcodes, swapping is not allowed in address pins.

                   

                  What is the situation in parallel NOR Flash (and also in SRAM and SDRAM)

                  This is what i wanna learn in shortly. Since i am hardware guy i have no idea about flash driver.

                   

                  Pls encourage me into an easy way.

                   

                  Regards

                  • 6. Re: Pin swapping in parallel-interface memory types
                    BushraH_91

                    Hello,

                    We are not sure if we really understand the question.

                     

                    Regard to parallel NOR, there is no swap mechanism within the chip. That’s is to say, if swapping address or data pins, it has to be handled by CPU side either hardware or software to guarantee correct address/data arrive at flash pins. Let’s have a simple example below:

                    CPU wants to access flash address 10b:

                    without address swap, CPU sends bit “0” on A0 and flash A0 gets bit “0”; CPU sends bit “1” on A1 and flash A1 gets bit “1”, then flash address 10b is accessed.

                    with address swap CPU A0 connects to flash A1, and CPU A1 connects to flash A0, then to access flash address 10b, CPU needs to send bit “0” on A1 and flash A0 gets bit “0”; and CPU sends bit “1” on A0 and flash A1 gets bit “1”.

                     

                    This conversion/mapping needs to be done at CPU side by either hardware/or software to guarantee address “10” sent to flash A1A0.

                     

                    Same data bus conversion/mapping also needs to be handled if swapping data pins.

                     

                    Many parallel NOR commands are sending specific data to specific address,  example, 1st cycle needs to send data 0xAA to address 0xXXXXX555, 2nd cycle send data 0x55 to address 0xXXXXX2AA, … …, if any of the data or address in the command sequence is not correct (the address and/or data received at flash pins), then the command will be ignored.

                     

                    Thank you

                    Regards,

                    Bushra