5 Replies Latest reply on Apr 2, 2019 11:28 PM by VasanthR_91

    Implementation internally of 'sticky' status register

    RiAs_1660756

      Me again with the silly questions.  Perhaps someone with a bit of time on their hands could assist?

       

      My design compiles if the latch is transparent but not if it is sticky.  The design is rather full.  My first question is: is the hardware implementation in Figure 1 of the datasheet (Document Number: 001-96683 Rev. *A, page 3) the actual hardware implementation inside the chip?  If so, surely it should make no difference if the mode signal is high or low?  Or does that create issues in creating the mode signal for selective inputs?

       

      This leads me to a more general question: if the router fails, what strategies can I adopt to assist it in achieving a successful routing?

       

      For example, if a port pin is bit 4, say, is it better to take it to the bit 4 input of a status register rather than, say, bit 0?

       

      Is it better to route a pin to a status register and use that to issue an interrupt, or to put an interrupt component on the pin or just to use the pin's interrupt?  Or does the router resolve any of those to the same result?

       

      Is it better to use fewer clocks and route them to the components that need them or to use individual clocks albeit at the same frequency?

       

      Maybe there is a cool document that has a raft of neat tricks that can be used or has a list of space-reclaiming strategies for when designs refuse to route.  Does anyone know?

       

      Profound thanks to anyone who takes an interest!

       

      Richard.