In PSoC5 most of the components are made using UDBs and a hardware definition language named Warp Verilog. Usually there are no (or few) restrictions in routing components to pins, Can you please post your complete project so that we all can have a look at all of your settings. To do so, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file.
Thanks for replying to my posting.
Company policy prevents me from sharing design files. However, my query was a general one, not related specifically to my current project.
My questions amount to this: when I get Error M0004, what, in general, should I try, other than trial-and-error, to improve the router's chances of success?
In my view, the most scarce resource of PSoC is the routing, once it comes to ~80%, the project is at its limits. Try to unlock i/o pins and let Creator to assign pins by itself (Clean and Build option). As to the "sticky" option of the Ststus Register, try to attach the BUS_CLK to it instead of wiring-in some other clock.
Thank you for the suggestions. The first one is unavailable as the hardware is complete - but it was more-or-less how the pins were allocated at the design stage anyway. However, the second is worth a try.
At the moment, the circuit is fine. It uses a lot of the 5888's capability and does everything I need it to. However, I am in the position you describe where the project is nearing the limit of what can be accommodated.
I find that I can make a tiny change and it won't route. Using the interrupt associated with a pin will cause it to fail. If I put a signal to one input of a status register, it fails; the adjacent input and it routes. If I change the PLL to 48MHz, it fails; 36MHz it routes.
This suggests to me that there may be strategies that can be used to get out of jail. Your suggestion to use the bus clock is exactly what I am talking about.
As there is no project attached, you can follow the best design practices for PSoC5 devices in this document: https://www.cypress.com/documentation/application-notes/an81623-psocr-3-psoc-4-and-psoc-5lp-digital-design-best-practices .
Extending response 4, we would add that it is preferable to use as few unique clocks as possible because different clocks can introduce placement constraints.