9 Replies Latest reply on Mar 25, 2019 3:01 AM by pemic_632601

    CY8C4245 SWD acquisition




      I am trying to program the CY8C4245 via SWD interface.


      I implement it in accordance with the programming specifications document



      But I encountered a problem in the Acquisition sequence (figure 4-3 in the specs). The last step I am able to correctly do is the Check Test Mode, it returns correct value.


      But when I try to do another step (Poll SROM_PRIVILIGED_BIT), the ACK of the second Read_DAP in this step always returns FAULT.


      When I try to read CTRL/STAT register after this, it returns 0xF4000020, STICKYERR is set.


      This happens always, it does not depend on the communication frequency used.


      The CY8C4245 I communicate with is alone MCU soldered on a PCB with several decoupling capacitors only.


      What could be wrong?

        • 1. Re: CY8C4245 SWD acquisition



          You can program PSoC4 via SWD using any scripts provided at this path in your system:

          C:\Program Files (x86)\Cypress\Programmer\Examples\Programming\PSoC4\SWD


          You can get CLI commands to program, details can be obtained at this path:

          C:\Program Files (x86)\Cypress\Programmer\Documents


          Please attach the code used to program.

          • 2. Re: CY8C4245 SWD acquisition



            I have checked my code with this, I do not see there a difference:



            My code:


            // init




            Vcc(true); // switch on VCC

            Delay(10000); // 10ms


            // reset pulse


            Delay(100000); // 100ms


            Delay(10); // 10us


            // prog mode enter loop


              // send 53 ticks with D=1


              // send 2 ticks with D=0


              Delay(1); // 1 us

              // read DPIDR, does not exit when ACK=7

              ReadSWD_special(false, 0);


            until AckOK;


            if readdata<>$BB11477 then exit;



            // DP CTRL/STAT addr=4

            WriteSWD(false,$4, $54000000);

            // DP SELECT, addr=$8

            WriteSWD(false,$8, $00000000);

            //  AP CSW=00000002

            WriteSWD(true,$0, 2);

            // enter TEST_MODE

            // AP TAR, addr=0x4

            WriteSWD(true,$4, $40030014);

            // DRW

            WriteSWD(true,$C, $80000000);


            // check that there is set what I set in TEST_MODE

            data32:=SWDReadFromAddr($40030014, OK);

            if not OK then exit;

            if data32 and $80000000 <> $80000000 then exit;



            // Poll SROM PRIVILEGED bit

            // --------------------




                 // HERE is the problem

                 data32:=SWDReadFromAddr($40000004, OK);

                 if not OK then exit;



                 if i>1000 then exit; // timeout

            until data32 and $10000000=0;

            // --------------------




            SWDReadFromAddr does this:

              WriteSWD(true,$4, Addr);

              // read AP DRW, addr=0xC

              ReadSWD(true, $C);

              // read AP DRW, addr=0xC

              ReadSWD(true, $C);


            The second ReadSWD returns ACK=FAULT when I call

            SWDReadFromAddr($40000004, OK);

            All steps before was OK, ACKs=OK, correct values returned.



            Thank you.

            • 3. Re: CY8C4245 SWD acquisition



              For the AN84858, please check the doc available at this link:



              There are certain macros values that need to be calculated according to the host  used to program PSoC.

              Please check topics "5.Calculating HSSP Timeout Parameters" from page#9-11


              Please check if your code is complying to that timeouts.



              • 4. Re: CY8C4245 SWD acquisition



                It says that the Device_acquire_timeout is 1.5ms, in my case as I can see on a logic analyzer, this sequence is done in 1.430ms, it is always the similar time.



                Concerning the  SROM_POLLING_TIMEOUT, it returns FAULT in the first throughpass of the loop.


                I can read from other addresses of the MCU, it communicates with me, it has problem with this concrete address.


                Or does the 1s timeout in this case mean, that the MCU repeatedly returns FAULT and later, in 1 s, it will return a correct value and ACK=OK?

                I have not tried this, it would be really strange.

                • 5. Re: CY8C4245 SWD acquisition



                  Is there anything new concerning this?


                  I believe that in Cypress there should be somebody able to help with this.


                  Thank you.

                  • 6. Re: CY8C4245 SWD acquisition



                    Although I'm not totally understanding the SWD protocol,

                    in my customer support experience with other MCUs,

                    when a newly built board fails to start up,

                    it was often caused by the absence of an external pull-up resistor of the nRESET signal.


                    As you wrote

                    > The CY8C4245 I communicate with is alone MCU soldered on a PCB with several decoupling capacitors only.


                    In case you have not applied the pull-up resistor, how about adding a resistor and a capacitor like below?



                    In case, I'm totally wrong, I'm very sorry (in advance).



                    • 7. Re: CY8C4245 SWD acquisition

                      The programming spec referenced in original message is very old and has been replaced with:


                      I would also suggest purchasing the KIT-049-4200.  It's lessthan $10 and has SWD pinned out to through-holes for easy access.  It also has a UART-USB interface to program from PC.  I mention this KIT since it's known hardware to work right out of the box.  It would verify your downloading scripts.  The downside is, if you over-write the bootloader, you'll need to reprogram it with either Miniprog3 and a KitProg.  Then again, it might not matter if you clobber the bootloader.  The goal is to debug/verify your scripts with this KIT and then transfer that knowledge to your hardware design.



                      You can also check your hardware design against KIT-049-4200 since it also uses the CY8C4245 chip.


                      I forgot to mention, there's a great article on how to use KIT-049-4200 to program another KIT-049-4200 via SWD.  The source files are available at

                      KBA93541.   You can compare these scripts against your scripts.

                      Using the CY8CKIT-049 to Program Another PSoC® 4 - KBA93541


                      BTW, what hardware are you using as the interface to SWD?



                      • 8. Re: CY8C4245 SWD acquisition

                        "data32:=SWDReadFromAddr($40000004, OK);

                            if not OK then exit;



                        This delay of 1000ms is defined by  SROM_POLLING_TIMEOUT in AN84858.This macro signifies the number of times CPUSS_SYSREQ can be read and checked if SROM_SYSREQ_BIT and SROM_PRIVILEGED_BIT are set to 0 in a 1-second interval.

                        This macro's value need to be calculated for the Host MCU in AN84858, that is used to program PSoC

                        • 9. Re: CY8C4245 SWD acquisition



                          Thanks to all.


                          Bill, thank you for the link to the new document.