7 Replies Latest reply on Mar 12, 2019 7:09 AM by HemanthR_06

    AN65974 example design not working without any user modification


      I am trying to bring up the AN65974 example design with the SP601 XILINX board and CYUSB3KIT-003. I am using both SDK files and FPGA bit file as is. I am trying to test the loopback mode as described at the application note. The switches on the SP601 board are as explained at the note (1,3 ON , 2,4 OFF). Jumper J5 is open, the rest are closed. The image I download to the FX3 is the "SF_loopback.img" located at the ../FX3 Firmware\SlaveFifoSync\Release folder.


      But, I am getting the 997 timeout error when trying to do the BULK IN transfer after sending the TEXT.TXT file as BULK OUT.

      When I ran into these problems, I opened the XILINX project provided with the AN65974  and added a Chipscope Core. I observe no bus activity whatsoever between the FPGA and the FX3 during the first stage (BULK OUT)  when I am sending the TEST.TXT file. This explains the fact that nothing comes back...


      Please advise what am I missing here.